Manash Baral
@manash__baral
Electronics & Communication Engineering Student | Passionate about PCB Design, Automation & Robotics | Exploring, building & sharing ideas daily
Concluding my 30-day learning challenge! 🚀 Over the past month, I explored the world of Verilog HDL — from basic gates, modeling styles, and flip-flops to counters, encoders, decoders, testbenches, and VCD files. #FeastivalOfLearning #LearningUtsav2025 @learning_utsav
#LUD30 of #LearningUtsav2025 🎓 Day 30 of my learning journey — explored VCD (Value Change Dump) in #Verilog, which helps record signal changes during simulation for waveform analysis. A key step in understanding design behavior visually. #FPGA #VLSI #FestivalOfLearning
#LUD29 of #LearningUtsav2025 🎯 Today, I explored namespace in #Verilog, understanding how it helps organize code, prevent naming conflicts, and improve module hierarchy and readability. #FPGA #VLSI #HDL #DigitalDesign #FeastivalOfLearning
#LUD28 of #LearningUtsav2025 🎓 Today, I practiced coding the Priority Encoder in #Verilog. It was great to understand how the encoder prioritizes the highest-order input signal and outputs its binary code. 💡 #FPGA #VLSI #DigitalDesign #HDL #FestivalOfLearning
#LUD27 of #LearningUtsav2025 🎯 Today, I practiced coding the Gray Counter in #Verilog. It was great to understand how binary counters can be converted to Gray code for minimizing transition errors in digital systems. #FPGA #VLSI #FeastivalOfLearning
#LUD26 of #LearningUtsav2025 🎯 Today, I practiced coding a 4-bit counter in #Verilog. Gained hands-on experience with sequential logic and clock-based state transitions — a key step in digital design! ⚙️ #FPGA #VLSI #HDL #FeastivalOfLearning
#LUD25 of #LearningUtsav2025 Today, I coded the JK Flip-Flop in #Verilog Explored how the JK flip-flop eliminates the invalid state of SR flip-flop and toggles output when both inputs are high. Gained better understanding sequential logic design #VLSI #FPGA #FeastivalOfLearning
#LUD24 of #LearningUtsav2025 🎯 Today, I coded the 7-segment display in #Verilog. Learned how to map binary inputs to display digits (0–9) by controlling individual LED segments efficiently. 💡 #FPGA #VLSI #DigitalDesign #HDL #Electronics #FestivalOfLearning
#LUD23 of #LearningUtsav2025 Continuing my journey into Verilog testbenches — today I wrote a test bench for the Full Adder circuit to simulate and verify its behavior. Gaining more confidence in writing structured test environments! ⚙️💻 #Verilog #FPGA #VLSI #FestivalOfLearning
#LUD22 of #LearningUtsav2025 🎓 Today, I explored the callback function in #Verilog — a powerful concept used to execute specific tasks automatically in response to events, enhancing modularity and simulation control. #FPGA #VLSI #HDL #FestivalOfLearning
#LUD21 of #LearningUtsav2025 🎓 Today, I started learning about writing testbenches in #Verilog — understanding how to simulate and verify digital designs effectively before hardware implementation. Excited to explore more on verification! ⚙️ #FPGA #VLSI #FestivalOfLearning
#LUD20 of #LearningUtsav2025 🎯 Today, I practiced Verilog coding on HDLBits, solving hands-on exercises that strengthened my understanding of hardware design concepts. Each challenge helped me think like a real chip designer! #Verilog #FPGA #VLSI #HDL #FestivalOfLearning
#LUD19 of #LearningUtsav2025 Today, I explored Tasks and Functions in #Verilog. Learned how they enhance code reusability, modularity, and debugging. Understood that tasks can include delays & multiple outputs, while functions return a single value. #FPGA #FeastivalOfLearning
#LUD18 of #LearningUtsav2025 Today, I learned about Compiler Directives and System Tasks in #Verilog. Compiler directives like define and include help control compilation, while system tasks such as $display and $finish are used for simulation and debugging. #FestivalOfLearning
#LUD17 of #LearningUtsav 🎯 Explored behavioral modeling in #Verilog. Learned about blocking (=) & non-blocking (<=), initial & always blocks, begin–end, fork–join, branching statements, and loops. #FPGA #VLSI #DigitalDesign #FestivalOfLearning
#LUD16 of #LearningUtsav2025 🎯 Today, I explored dataflow modeling in Verilog — a method to describe circuits using logical and arithmetic expressions. It helps visualize how data flows through the design! ⚙️💡 #Verilog #FPGA #VLSI #DigitalDesign #FestivalOfLearning
#LUD15 of #LearningUtsav2025 ⚙️ Today, I dived deep into Gate-Level Modeling in Verilog and implemented it in basic circuits. Explored logic gates like AND, OR, NOT, BUF, BUFI, NOTIF, understanding how digital logic works from the ground up. #Verilog #FPGA #FestivalOfLearning
#LUD14 of #LearningUtsav2025 ⚡ Today, I gained insight into memory, parameters, and strings in Verilog. Learned how parameters help create flexible designs, memory stores data efficiently, and strings make debugging easier. #Verilog #FPGA #HDL #FestivalOfLearning
#LUD13 of #LearningUtsav2025 Today I explored vectors and arrays in Verilog, learning how to define and use multi-dimensional arrays effectively. It’s amazing how structured data handling can simplify complex digital designs! ⚡💻 #Verilog #HDL #FPGA #VLSI #FestivalOfLearning
#LUD12 of #LearningUtsav2025 🎓 Learned about net & reg data types in Verilog. Explored wand (wired-AND) & wor (wired-OR) for multi-driver signals, number usage, and various reg types with their storage behavior. #Verilog #HDL #FPGA #VLSI #FestivalOfLearning
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