#riscvsummit search results

Milk-V Megrez running AMD 7900XTX Quad core SiFive P550, 19.95TOPS NPU #riscv #RISCVSummit

MilkV_Official's tweet image. Milk-V Megrez running AMD 7900XTX

Quad core SiFive P550, 19.95TOPS NPU

#riscv #RISCVSummit
MilkV_Official's tweet image. Milk-V Megrez running AMD 7900XTX

Quad core SiFive P550, 19.95TOPS NPU

#riscv #RISCVSummit

.@EDNcom's Majeed Ahmad recapped #RISCVSummit, highlighting key trends and updates, including the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems, as well as insights into RISC-V’s design ecosystem: hubs.la/Q03Sqy990

risc_v's tweet image. .@EDNcom's Majeed Ahmad recapped #RISCVSummit, highlighting key trends and updates, including the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems, as well as insights into RISC-V’s design ecosystem: hubs.la/Q03Sqy990

If you are at #riscvsummit drop by our booth! @Ainekk0 is finally out of stealth and wants to make as many friends as possible!

rhatr's tweet image. If you are at #riscvsummit drop by our booth! @Ainekk0 is finally out of stealth and wants to make as many friends as possible!

DeepComputing just launched the RISC-V Support Programs at the #RISCVSummit NA — empowering students, educators & developers to explore open hardware and innovation. If you’re interested in joining or learning more, visit 👉 deepcomputing.io/deepcomputing-… We’re excited to already have…

DeepComputingio's tweet image. DeepComputing just launched the RISC-V Support Programs at the #RISCVSummit NA — empowering students, educators & developers to explore open hardware and innovation.
If you’re interested in joining or learning more, visit 👉 deepcomputing.io/deepcomputing-…
We’re excited to already have…

At #RISCVSummit North America 2025, DeepComputing Founder & CEO @Yuning_XC5 will share how we’re bringing intelligent media experiences to life on RISC-V AI SoCs. Join us to explore how RISC-V is redefining the way AI applications run at the edge and beyond. #RISCV

DeepComputingio's tweet image. At #RISCVSummit North America 2025, DeepComputing Founder & CEO @Yuning_XC5 will share how we’re bringing intelligent media experiences to life on RISC-V AI SoCs.

Join us to explore how RISC-V is redefining the way AI applications run at the edge and beyond.

#RISCV…

Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀

DeepComputingio's tweet image. Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀
DeepComputingio's tweet image. Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀
DeepComputingio's tweet image. Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀
DeepComputingio's tweet image. Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀

🎉 Raffle at RISC-V Summit North America! 🎉 DeepComputing is excited to bring the DC-ROMA RISC-V AI PC to Santa Clara! 🚀 And we’ve prepared a special raffle for our community! Don’t miss the chance—visit us at RISC-V Summit NA and win big! #RISCVSummit #RISCV #AI

DeepComputingio's tweet image. 🎉 Raffle at RISC-V Summit North America! 🎉

DeepComputing is excited to bring the DC-ROMA RISC-V AI PC to Santa Clara! 
🚀 And we’ve prepared a special raffle for our community!

Don’t miss the chance—visit us at RISC-V Summit NA and win big!

#RISCVSummit #RISCV #AI…

During #RISCVSummit, we announced a major milestone: RISC-V International is now approved as a recognized Publicly Available Specification (PAS) Submitter by the ISO/IEC Joint Technical Committee (JTC 1)! No other ISA has ever attained this status. Learn more:…

risc_v's tweet image. During #RISCVSummit, we announced a major milestone: RISC-V International is now approved as a recognized Publicly Available Specification (PAS) Submitter by the ISO/IEC Joint Technical Committee (JTC 1)! No other ISA has ever attained this status. Learn more:…

🎥The wait is over! All RISC-V Summit North America sessions are now available on RISC-V International’s official YouTube channel! Catch all sessions on our channel now: youtube.com/playlist?list=… #RISCVSummit #RISCVEverywhere

risc_v's tweet image. 🎥The wait is over! All RISC-V Summit North America sessions are now available on RISC-V International’s official YouTube channel! Catch all sessions on our channel now: youtube.com/playlist?list=… #RISCVSummit #RISCVEverywhere

🚗 NEXT WEEK at #RISCVSummit North America: Winning the Future of RISC-V Automotive MCU Through Ecosystem Collaboration and Open Standards For Infineon Technologies — one of the world’s largest automotive semiconductor suppliers — the future of automotive is based on RISC-V.…

risc_v's tweet image. 🚗 NEXT WEEK at #RISCVSummit North America: Winning the Future of RISC-V Automotive MCU Through Ecosystem Collaboration and Open Standards  

For Infineon Technologies — one of the world’s largest automotive semiconductor suppliers — the future of automotive is based on RISC-V.…

RISC-V Ambassador @FlorianWoh is on site at RISC-V Summit North America! Missing the action? Stop by and register at the door. #RISCVSummit


According to The SHD Group, RISC-V is projected to be in over 35B SoCs by 2031, representing an estimated $300B in revenue. At #RISCVSummit, Richard Wawrzyniak shared more about how RISC-V is growing beyond expectations. Check out our site for more about the momentum of RISC-V:…

risc_v's tweet image. According to The SHD Group, RISC-V is projected to be in over 35B SoCs by 2031, representing an estimated $300B in revenue. At #RISCVSummit, Richard Wawrzyniak shared more about how RISC-V is growing beyond expectations. Check out our site for more about the momentum of RISC-V:…

Drop by the #Tenstorrent booth at the #RISCVSummit and play #DOOM on our Ascalon #RISCV CPU running on a #Synopsys HAPS emulator. Are we the only CPU to run DOOM in pre silicon test? It’s uncovered bugs in GCC, QEMU, and our own RTL.

antonblanchard's tweet image. Drop by the #Tenstorrent booth at the #RISCVSummit and play #DOOM on our Ascalon #RISCV CPU running on a #Synopsys HAPS emulator. Are we the only CPU to run DOOM in pre silicon test? It’s uncovered bugs in GCC, QEMU, and our own RTL.

The dev zone at #RISCVSummit was crammed full of interesting things and very popular this week, here I chat to Austin @risc_v about the #HPC #RISCV demo we had brought from @EPCCed . Thanks to Carl for providing the hardware and installing things!


RISC-V Summit North America 2025に来てます🇺🇸 #RISCVSummit #RISCVEverywhere

Cra2yPierr0t's tweet image. RISC-V Summit North America 2025に来てます🇺🇸

#RISCVSummit #RISCVEverywhere

The RISC-V Vector Extension (RVV) is a critical capability for many important applications, and Breker Verification Systems’ Brian Barker discussed why at #RISCVSummit earlier today. Brian believes that RISC-V can evolve to cover DSP, GPU, and machine learning without an…

risc_v's tweet image. The RISC-V Vector Extension (RVV) is a critical capability for many important applications, and Breker Verification Systems’ Brian Barker discussed why at #RISCVSummit earlier today.

Brian believes that RISC-V can evolve to cover DSP, GPU, and machine learning without an…
risc_v's tweet image. The RISC-V Vector Extension (RVV) is a critical capability for many important applications, and Breker Verification Systems’ Brian Barker discussed why at #RISCVSummit earlier today.

Brian believes that RISC-V can evolve to cover DSP, GPU, and machine learning without an…
risc_v's tweet image. The RISC-V Vector Extension (RVV) is a critical capability for many important applications, and Breker Verification Systems’ Brian Barker discussed why at #RISCVSummit earlier today.

Brian believes that RISC-V can evolve to cover DSP, GPU, and machine learning without an…

Learn how trust and innovation can co-exist with secure, deterministic RISC-V® solutions for the world’s toughest missions. Join technical fellow Ted Speers for his keynote at RISC-V Summit North America 2025. Register now: mchp.us/4p91708. @risc_v #RISCVSummit


Had a great time at the #RISCVSummit 2025, thanks very much to @risc_v for the invitation to give a keynote talk about #RISCV in #HPC, was an honour and I also very much enjoyed being a panelist at the @Google breakfast and presenting #HPC #RISCV updates during the member's day

NickBrownHPC's tweet image. Had a great time at the #RISCVSummit 2025, thanks very much to @risc_v for the invitation to give a keynote talk about #RISCV in #HPC, was an honour and I also very much enjoyed being a panelist at the @Google breakfast and presenting #HPC #RISCV updates during the member's day
NickBrownHPC's tweet image. Had a great time at the #RISCVSummit 2025, thanks very much to @risc_v for the invitation to give a keynote talk about #RISCV in #HPC, was an honour and I also very much enjoyed being a panelist at the @Google breakfast and presenting #HPC #RISCV updates during the member's day
NickBrownHPC's tweet image. Had a great time at the #RISCVSummit 2025, thanks very much to @risc_v for the invitation to give a keynote talk about #RISCV in #HPC, was an honour and I also very much enjoyed being a panelist at the @Google breakfast and presenting #HPC #RISCV updates during the member's day
NickBrownHPC's tweet image. Had a great time at the #RISCVSummit 2025, thanks very much to @risc_v for the invitation to give a keynote talk about #RISCV in #HPC, was an honour and I also very much enjoyed being a panelist at the @Google breakfast and presenting #HPC #RISCV updates during the member's day

Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀 Provides open source SDK, U-boot, and Linux Kernel. See you in #RISCVSummit 2023 China! #riscv For more details: community.milkv.io/t/milk-v-launc…

MilkV_Official's tweet image. Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀

Provides open source SDK, U-boot, and Linux Kernel.

See you in #RISCVSummit 2023 China!
#riscv 

For more details: community.milkv.io/t/milk-v-launc…
MilkV_Official's tweet image. Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀

Provides open source SDK, U-boot, and Linux Kernel.

See you in #RISCVSummit 2023 China!
#riscv 

For more details: community.milkv.io/t/milk-v-launc…
MilkV_Official's tweet image. Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀

Provides open source SDK, U-boot, and Linux Kernel.

See you in #RISCVSummit 2023 China!
#riscv 

For more details: community.milkv.io/t/milk-v-launc…
MilkV_Official's tweet image. Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀

Provides open source SDK, U-boot, and Linux Kernel.

See you in #RISCVSummit 2023 China!
#riscv 

For more details: community.milkv.io/t/milk-v-launc…

That’s a wrap on #RISCVSummit 2025! A huge thank you to everyone who contributed to making the event so incredible. Let’s continue to build the future of innovation on RISC-V together. #RISCVEverywhere! Thank you to our Diamond Sponsors: DAMO Academy Xiantie and @MicrochipTech.…

risc_v's tweet image. That’s a wrap on #RISCVSummit 2025! A huge thank you to everyone who contributed to making the event so incredible. Let’s continue to build the future of innovation on RISC-V together. #RISCVEverywhere!

Thank you to our Diamond Sponsors: DAMO Academy Xiantie and @MicrochipTech.…
risc_v's tweet image. That’s a wrap on #RISCVSummit 2025! A huge thank you to everyone who contributed to making the event so incredible. Let’s continue to build the future of innovation on RISC-V together. #RISCVEverywhere!

Thank you to our Diamond Sponsors: DAMO Academy Xiantie and @MicrochipTech.…
risc_v's tweet image. That’s a wrap on #RISCVSummit 2025! A huge thank you to everyone who contributed to making the event so incredible. Let’s continue to build the future of innovation on RISC-V together. #RISCVEverywhere!

Thank you to our Diamond Sponsors: DAMO Academy Xiantie and @MicrochipTech.…
risc_v's tweet image. That’s a wrap on #RISCVSummit 2025! A huge thank you to everyone who contributed to making the event so incredible. Let’s continue to build the future of innovation on RISC-V together. #RISCVEverywhere!

Thank you to our Diamond Sponsors: DAMO Academy Xiantie and @MicrochipTech.…

.@EDNcom's Majeed Ahmad recapped #RISCVSummit, highlighting key trends and updates, including the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems, as well as insights into RISC-V’s design ecosystem: hubs.la/Q03Sqy990

risc_v's tweet image. .@EDNcom's Majeed Ahmad recapped #RISCVSummit, highlighting key trends and updates, including the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems, as well as insights into RISC-V’s design ecosystem: hubs.la/Q03Sqy990

At @eetimes, The Linux Foundation's Daniela Barbosa discussed a new approach: combining the openness of RISC-V with blockchain. Read more about this use case that Daniela presented at #RISCVSummit: hubs.la/Q03Rp6460 #RISCVEverywhere #Blockchain

risc_v's tweet image. At @eetimes, The Linux Foundation's Daniela Barbosa discussed a new approach: combining the openness of RISC-V with blockchain. Read more about this use case that Daniela presented at #RISCVSummit: hubs.la/Q03Rp6460  #RISCVEverywhere #Blockchain

Thanks @risc_v for the invite to give a keynote at #RISCVSummit a couple of weeks ago. We have seen great progress in #RISCV for #HPC, and given promises by vendors and progress in the sw ecosystem I predict that 2026 could be a watershed year. youtu.be/ItA-NS4vxsU?si…

NickBrownHPC's tweet card. Keynote: Reimagining the Future of High Performance Computing...

youtube.com

YouTube

Keynote: Reimagining the Future of High Performance Computing...


🎥The wait is over! All RISC-V Summit North America sessions are now available on RISC-V International’s official YouTube channel! Catch all sessions on our channel now: youtube.com/playlist?list=… #RISCVSummit #RISCVEverywhere

risc_v's tweet image. 🎥The wait is over! All RISC-V Summit North America sessions are now available on RISC-V International’s official YouTube channel! Catch all sessions on our channel now: youtube.com/playlist?list=… #RISCVSummit #RISCVEverywhere

felix86 25.11 is now released, bringing SSE 4.2 support and more optimizations! felix86.com/felix86-25-11/ We also had a presentation at #RISCVSummit. It is now on YouTube and talks about some low-level translation details. You can watch it here: youtube.com/watch?v=S_NkVB…

felix86_emu's tweet card. RISC-V for Gaming: Emulating X86 on RISC-V - Paris Oplopoios, felix86

youtube.com

YouTube

RISC-V for Gaming: Emulating X86 on RISC-V - Paris Oplopoios, felix86


During #RISCVSummit, we announced a major milestone: RISC-V International is now approved as a recognized Publicly Available Specification (PAS) Submitter by the ISO/IEC Joint Technical Committee (JTC 1)! No other ISA has ever attained this status. Learn more:…

risc_v's tweet image. During #RISCVSummit, we announced a major milestone: RISC-V International is now approved as a recognized Publicly Available Specification (PAS) Submitter by the ISO/IEC Joint Technical Committee (JTC 1)! No other ISA has ever attained this status. Learn more:…

No results for "#riscvsummit"

Milk-V Megrez running AMD 7900XTX Quad core SiFive P550, 19.95TOPS NPU #riscv #RISCVSummit

MilkV_Official's tweet image. Milk-V Megrez running AMD 7900XTX

Quad core SiFive P550, 19.95TOPS NPU

#riscv #RISCVSummit
MilkV_Official's tweet image. Milk-V Megrez running AMD 7900XTX

Quad core SiFive P550, 19.95TOPS NPU

#riscv #RISCVSummit

RISC-V Summit North America 2025に来てます🇺🇸 #RISCVSummit #RISCVEverywhere

Cra2yPierr0t's tweet image. RISC-V Summit North America 2025に来てます🇺🇸

#RISCVSummit #RISCVEverywhere

If you are at #riscvsummit drop by our booth! @Ainekk0 is finally out of stealth and wants to make as many friends as possible!

rhatr's tweet image. If you are at #riscvsummit drop by our booth! @Ainekk0 is finally out of stealth and wants to make as many friends as possible!

Flo Wohlrab presents the #OpenHW Foundation at #RISCVSummit North America! #RISCVEverywhere

OpenHWFdn's tweet image. Flo Wohlrab presents the #OpenHW Foundation at #RISCVSummit North America! 

#RISCVEverywhere
OpenHWFdn's tweet image. Flo Wohlrab presents the #OpenHW Foundation at #RISCVSummit North America! 

#RISCVEverywhere

During #RISCVSummit, we announced a major milestone: RISC-V International is now approved as a recognized Publicly Available Specification (PAS) Submitter by the ISO/IEC Joint Technical Committee (JTC 1)! No other ISA has ever attained this status. Learn more:…

risc_v's tweet image. During #RISCVSummit, we announced a major milestone: RISC-V International is now approved as a recognized Publicly Available Specification (PAS) Submitter by the ISO/IEC Joint Technical Committee (JTC 1)! No other ISA has ever attained this status. Learn more:…

🚗 NEXT WEEK at #RISCVSummit North America: Winning the Future of RISC-V Automotive MCU Through Ecosystem Collaboration and Open Standards For Infineon Technologies — one of the world’s largest automotive semiconductor suppliers — the future of automotive is based on RISC-V.…

risc_v's tweet image. 🚗 NEXT WEEK at #RISCVSummit North America: Winning the Future of RISC-V Automotive MCU Through Ecosystem Collaboration and Open Standards  

For Infineon Technologies — one of the world’s largest automotive semiconductor suppliers — the future of automotive is based on RISC-V.…

.@EDNcom's Majeed Ahmad recapped #RISCVSummit, highlighting key trends and updates, including the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems, as well as insights into RISC-V’s design ecosystem: hubs.la/Q03Sqy990

risc_v's tweet image. .@EDNcom's Majeed Ahmad recapped #RISCVSummit, highlighting key trends and updates, including the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems, as well as insights into RISC-V’s design ecosystem: hubs.la/Q03Sqy990

🗓️ Hard to believe it’s already October, which means #RISCVSummit is right around the corner! Register now to secure your spot: hubs.la/Q03Ns3gQ0 The agenda continues to grow, with new sessions from industry leaders like @awscloud and many more. Explore the schedule:…

risc_v's tweet image. 🗓️ Hard to believe it’s already October, which means #RISCVSummit is right around the corner! Register now to secure your spot: hubs.la/Q03Ns3gQ0

The agenda continues to grow, with new sessions from industry leaders like @awscloud and many more. Explore the schedule:…
risc_v's tweet image. 🗓️ Hard to believe it’s already October, which means #RISCVSummit is right around the corner! Register now to secure your spot: hubs.la/Q03Ns3gQ0

The agenda continues to grow, with new sessions from industry leaders like @awscloud and many more. Explore the schedule:…
risc_v's tweet image. 🗓️ Hard to believe it’s already October, which means #RISCVSummit is right around the corner! Register now to secure your spot: hubs.la/Q03Ns3gQ0

The agenda continues to grow, with new sessions from industry leaders like @awscloud and many more. Explore the schedule:…

DeepComputing just launched the RISC-V Support Programs at the #RISCVSummit NA — empowering students, educators & developers to explore open hardware and innovation. If you’re interested in joining or learning more, visit 👉 deepcomputing.io/deepcomputing-… We’re excited to already have…

DeepComputingio's tweet image. DeepComputing just launched the RISC-V Support Programs at the #RISCVSummit NA — empowering students, educators & developers to explore open hardware and innovation.
If you’re interested in joining or learning more, visit 👉 deepcomputing.io/deepcomputing-…
We’re excited to already have…

Milk-V Meles and NAS! #riscv #riscvsummit

MilkV_Official's tweet image. Milk-V Meles and NAS!

#riscv #riscvsummit

The XuanTie Partner Conference is this week, March 14! This year's theme, "Openness and Connectivity," promises enlightening insights and fruitful exchanges that will shape the future landscape of technology. You don’t want to miss this ➡️hubs.la/Q02nLFg20

risc_v's tweet image. The XuanTie Partner Conference is this week, March 14! This year's theme, "Openness and Connectivity," promises enlightening insights and fruitful exchanges that will shape the future landscape of technology.

You don’t want to miss this ➡️hubs.la/Q02nLFg20


🎉 Raffle at RISC-V Summit North America! 🎉 DeepComputing is excited to bring the DC-ROMA RISC-V AI PC to Santa Clara! 🚀 And we’ve prepared a special raffle for our community! Don’t miss the chance—visit us at RISC-V Summit NA and win big! #RISCVSummit #RISCV #AI

DeepComputingio's tweet image. 🎉 Raffle at RISC-V Summit North America! 🎉

DeepComputing is excited to bring the DC-ROMA RISC-V AI PC to Santa Clara! 
🚀 And we’ve prepared a special raffle for our community!

Don’t miss the chance—visit us at RISC-V Summit NA and win big!

#RISCVSummit #RISCV #AI…

RISC-V underpins billions of shipped cores, from tiny sensor devices to consumer computer components, right up to HPC. Whether you're just starting your RISC-V journey or looking to shape its global momentum, #RISCVSummit is the best place to be. 👉 hubs.la/Q03L-NC90

risc_v's tweet image. RISC-V underpins billions of shipped cores, from tiny sensor devices to consumer computer components, right up to HPC. Whether you're just starting your RISC-V journey or looking to shape its global momentum, #RISCVSummit is the best place to be. 👉 hubs.la/Q03L-NC90

Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀 Provides open source SDK, U-boot, and Linux Kernel. See you in #RISCVSummit 2023 China! #riscv For more details: community.milkv.io/t/milk-v-launc…

MilkV_Official's tweet image. Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀

Provides open source SDK, U-boot, and Linux Kernel.

See you in #RISCVSummit 2023 China!
#riscv 

For more details: community.milkv.io/t/milk-v-launc…
MilkV_Official's tweet image. Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀

Provides open source SDK, U-boot, and Linux Kernel.

See you in #RISCVSummit 2023 China!
#riscv 

For more details: community.milkv.io/t/milk-v-launc…
MilkV_Official's tweet image. Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀

Provides open source SDK, U-boot, and Linux Kernel.

See you in #RISCVSummit 2023 China!
#riscv 

For more details: community.milkv.io/t/milk-v-launc…
MilkV_Official's tweet image. Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch 🚀

Provides open source SDK, U-boot, and Linux Kernel.

See you in #RISCVSummit 2023 China!
#riscv 

For more details: community.milkv.io/t/milk-v-launc…

At #RISCVSummit North America 2025, DeepComputing Founder & CEO @Yuning_XC5 will share how we’re bringing intelligent media experiences to life on RISC-V AI SoCs. Join us to explore how RISC-V is redefining the way AI applications run at the edge and beyond. #RISCV

DeepComputingio's tweet image. At #RISCVSummit North America 2025, DeepComputing Founder & CEO @Yuning_XC5 will share how we’re bringing intelligent media experiences to life on RISC-V AI SoCs.

Join us to explore how RISC-V is redefining the way AI applications run at the edge and beyond.

#RISCV…

Drop by the #Tenstorrent booth at the #RISCVSummit and play #DOOM on our Ascalon #RISCV CPU running on a #Synopsys HAPS emulator. Are we the only CPU to run DOOM in pre silicon test? It’s uncovered bugs in GCC, QEMU, and our own RTL.

antonblanchard's tweet image. Drop by the #Tenstorrent booth at the #RISCVSummit and play #DOOM on our Ascalon #RISCV CPU running on a #Synopsys HAPS emulator. Are we the only CPU to run DOOM in pre silicon test? It’s uncovered bugs in GCC, QEMU, and our own RTL.

Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀

DeepComputingio's tweet image. Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀
DeepComputingio's tweet image. Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀
DeepComputingio's tweet image. Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀
DeepComputingio's tweet image. Day 1 of #RISCVSummit NA kicked off with an inspiring and hands-on workshop by Matt from @RedHat and Yuning @Yuning_XC5 from DeepComputing — Getting Started with RISC-V, Fedora, and AI! 💻🚀

Thank you @risc_v for an incredible #RISCVSummit! Great to connect with our ecosystem partners, BrainChip, Arteris, Baya Systems, proteanTecs & S2C EDA, and share Andes innovations in AI, security & next-gen RISC-V CPU IP. #RISCV #RISCVEverywhere

Andes_Tech's tweet image. Thank you @risc_v  for an incredible #RISCVSummit!
Great to connect with our ecosystem partners, BrainChip, Arteris, Baya Systems, proteanTecs & S2C EDA, and share Andes innovations in AI, security & next-gen RISC-V CPU IP.
#RISCV #RISCVEverywhere
Andes_Tech's tweet image. Thank you @risc_v  for an incredible #RISCVSummit!
Great to connect with our ecosystem partners, BrainChip, Arteris, Baya Systems, proteanTecs & S2C EDA, and share Andes innovations in AI, security & next-gen RISC-V CPU IP.
#RISCV #RISCVEverywhere
Andes_Tech's tweet image. Thank you @risc_v  for an incredible #RISCVSummit!
Great to connect with our ecosystem partners, BrainChip, Arteris, Baya Systems, proteanTecs & S2C EDA, and share Andes innovations in AI, security & next-gen RISC-V CPU IP.
#RISCV #RISCVEverywhere
Andes_Tech's tweet image. Thank you @risc_v  for an incredible #RISCVSummit!
Great to connect with our ecosystem partners, BrainChip, Arteris, Baya Systems, proteanTecs & S2C EDA, and share Andes innovations in AI, security & next-gen RISC-V CPU IP.
#RISCV #RISCVEverywhere

Discover how our secure SoC FPGAs and 64-bit RISC-V® solutions accelerate your development and empower your most ambitious designs. Join us at RISC-V Summit North America to meet with our experts. Learn more and register: mchp.us/3V1oRFB. @risc_v #RISCVSummit

MicrochipTech's tweet image. Discover how our secure SoC FPGAs and 64-bit RISC-V® solutions accelerate your development and empower your most ambitious designs. Join us at RISC-V Summit North America to meet with our experts. Learn more and register: mchp.us/3V1oRFB. @risc_v #RISCVSummit…

According to The SHD Group, RISC-V is projected to be in over 35B SoCs by 2031, representing an estimated $300B in revenue. At #RISCVSummit, Richard Wawrzyniak shared more about how RISC-V is growing beyond expectations. Check out our site for more about the momentum of RISC-V:…

risc_v's tweet image. According to The SHD Group, RISC-V is projected to be in over 35B SoCs by 2031, representing an estimated $300B in revenue. At #RISCVSummit, Richard Wawrzyniak shared more about how RISC-V is growing beyond expectations. Check out our site for more about the momentum of RISC-V:…

The Ventana Veyron V2 is a 192-core RISC-V server CPU designed for UCIe compute chiplets and domain-specific accelerator silicon integration servethehome.com/ventana-veyron… @VentanaMicro @risc_v #RISCVSummit @UCIexpress

ServeTheHome's tweet image. The Ventana Veyron V2 is a 192-core RISC-V server CPU designed for UCIe compute chiplets and domain-specific accelerator silicon integration servethehome.com/ventana-veyron… @VentanaMicro @risc_v #RISCVSummit @UCIexpress

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