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CMOS_SOI's profile picture.

UCL CMOS SOI

@CMOS_SOI

90Posts 16Followers 10Following
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UCL CMOS SOI
 @CMOS_SOI
Mar 29, 2013

#P1206 Aluminium deposited on batch, and process on hold for easter hollidays

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UCL CMOS SOI
 @CMOS_SOI
Feb 22, 2013

#P1206 wafers sent to IBS for p-type S&D implantation.

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UCL CMOS SOI
 @CMOS_SOI
Feb 8, 2013

#P1206 implanation: waiting an answer from IEMN...

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UCL CMOS SOI
 @CMOS_SOI
Feb 8, 2013

#P1206 Looking for a solution for the S&D ionic implantation...

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CMOS_SOI's profile picture.
UCL CMOS SOI
 @CMOS_SOI
Jan 22, 2013

#P1206 LITHO poly done...waiting for the etching...

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UCL CMOS SOI
 @CMOS_SOI
Dec 8, 2012

#P1206 LPCVD polysilicon deposited on the whole batch.

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CMOS_SOI's profile picture.
UCL CMOS SOI
 @CMOS_SOI
Dec 8, 2012

#P1206 ALD Al2O3 deposited on extremely thin SiO2 as gate dielectrics, trial on one wafer.

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UCL CMOS SOI
 @CMOS_SOI
Nov 26, 2012

#P1206 wafers came back from IBS. Next step is final gate oxidation & polysilicon deposition.

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UCL CMOS SOI
 @CMOS_SOI
Nov 9, 2012

#P1206 wafers are ready to be sent to IBS for the second channel implantation.

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UCL CMOS SOI
 @CMOS_SOI
Oct 16, 2012

#P1206 Wafers are in the Koyo furnace for MOS gate oxidation.

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UCL CMOS SOI
 @CMOS_SOI
Oct 11, 2012

#P1206 Silicon nitride deposition for membrane fabrication

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CMOS_SOI's profile picture.
UCL CMOS SOI
 @CMOS_SOI
Oct 11, 2012

#P1206 BOX etched to create PIN diode and TRAPPISTe device.

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CMOS_SOI's profile picture.
UCL CMOS SOI
 @CMOS_SOI
Oct 4, 2012

#P1206 LOCOS isolation performed on all wafers with two recipes for comparaison

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CMOS_SOI's profile picture.
UCL CMOS SOI
 @CMOS_SOI
Oct 4, 2012

#P1206 Experimenting a new recipe for LOCOS isolation

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CMOS_SOI's profile picture.
UCL CMOS SOI
 @CMOS_SOI
Oct 4, 2012

New CMOS process #P1206 started in June...(never too late to let you know :) )

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UCL CMOS SOI reposted
wladek60's profile picture.
Wladek Grabinski
 @wladek60
Mar 9, 2012

Asked if there were significant differences between finfet transistors and fully depleted SOI transistors - the... fb.me/1kfUeE5MU

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CMOS_SOI's profile picture.
UCL CMOS SOI
 @CMOS_SOI
Nov 23, 2011

#P1103 Great news,the UCL CMOS SOI is back on tracks. Threshold voltage are again back to normal values.... :-D

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UCL CMOS SOI
 @CMOS_SOI
Nov 11, 2011

#P1103 Contact Pad opening...process will be terminated on Monday 14/11

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UCL CMOS SOI
 @CMOS_SOI
Nov 4, 2011

#P1103 wafers are ready for contact pre-tests on monday.

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CMOS_SOI's profile picture.
UCL CMOS SOI
 @CMOS_SOI
Nov 2, 2011

#P1103 Doing the aluminium etching...it is much better today

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