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"Come sono geniali gli americani, te la mettono lì, la libertà è alla portata di tutti, come la chitarra. Ognuno suona come vuole, e tutti suonano come vuole la libertà" Estratto da "Storie del Signor G", 1991 Unico, speciale, inarrivabile Gaber.
In questa fogna di pennivendoli, guitti politicanti, ciarlatani televisivi e servi di potere: #Gaber #Venezuela
Lo vengo a sapere solo oggi, grandissima perdita
Ci lascia #FaustoAmodei. E con la sua dipartita se ne va un altro esponente, ora davvero tra gli ultimissimi, del cantautorato di lotta. Claudio Lolli, 2018 Paolo Ciarchi, 2019 Alberto D'Amico, 2020 Paolo Pietrangeli, 2021 Giovanna Marini, 2024 Fausto Amodei, 2025
Class 100 Cleanroom Shed I Built For Semiconductor R&D :)
we’re at World Science Fiction Convention #worldcon in #seattle this week! Come play chess or roam through the colossal cave adventure on a 1975 vintage 12bit computer (the DEC PDP-8/e) icm.museum #retrocomputing #vintagecomputing #retrogaming
Ring 0 is a highly-privileged state on CPUs. Negative Ring Levels have even *higher* privilege. You just haven’t heard of them. For X86, Ring -1 is Hardware Virtualization, Ring -2 is System Management Mode, Ring -3 is Intel ME / AMD PSP. Arm get's even weirder:
This is my RISC-V RV32I core written in Verilog 2005, running in the browser Verilog ~> Verilator ~> Emscripten ~> Wasm So many possibilities for emulatio on the web!
55 years ago Digital Equipment Corporation introduced the tiny PDP-8/e followed by the LAB-8/e version in 1971. Both low cost, expandable and very fun to program little 12 bit computers. #vintagecomputing #retrocomputing
MY RISC-V (~RV32I) core running 300+ lines of code for testing, all running smooth! This is emulated but after I have it working 100% under emulation I'll try and overcome the biggest obstacle yet, memory interfacing and organization in FPGA
Today we got music out of the PiDP-1. Yesterday we got the visual paper tape running, making progress...
My RISC-V core running on real hardware and comunicating through UART! The core is not yet finished but I needed some real world feedback to get some motivation : ))
Finally one year after getting an FPGA board I started my journey into learning Verilog. Now I'm trying to implement a simple RISC-V RV32I core and scale it up from there. I predict that the biggest hassle will be to implement a memory interface (with shared instructions/data)
Claude 3.7 + IDA MCP automatically reverse engineers Windows driver ctf I wrote without symbols(p1, p2). Proceeds to create structures and recreates source code(p3) with extreme accuracy compared to original source(p4). ~3mins fully automated
I wrote a quick new post on "Digital Hygiene". Basically there are some no-brainer decisions you can make in your life to dramatically improve the privacy and security of your computing and this post goes over some of them. Blog post link in the reply, but copy pasting below…
CPU vs FPGA - what an easy and well explanation in 25 seconds
Ken Thompson, co-creator of the C programming language, shares the origins of UNIX, stating, "I built it for me."
BREAKING: The Internet Archive has lost its appeal in Hachette v. Internet Archive, the long-running, closely watched copyright case over the scanning and lending of print library books. Full story to follow.
Dependency is replaced by one-liner, weekly traffic is reduced by 440GB
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