RISC-V International
@risc_v
RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community.
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Hands-on RISC-V Vector (RVV) workshop with Daniel Thompson from RISCstar! Learn RVV concepts, port C code, and push performance for ML, signal processing, cryptography & more. Limited seats → hubs.la/Q03LTfh90
EMASS has unveiled ECS-DoT, a 22nm microprocessor designed to bring milliWatt-scale intelligence directly to edge and IoT devices. Built on RISC-V, the ECS-DoT is ideal for: 🌟Wearables 🌟Drones 🌟Predictive maintenance systems 🔗 hubs.la/Q03L-Rj10
📈 RISC-V is exceeding expectations. New 2025 analysis reveals that RISC-V-enabled silicon solutions have surpassed 25% market penetration for the first time, with projections to exceed 20B units by 2031. RISC-V IP revenue is also on the rise, expected to surpass $2B by 2031,…
Bay Area developers, roll up your sleeves! Join us Wednesday, October 22 for a full day of hands-on #RISCV workshops. Check out the full agenda for both Hardware and Software tracks: hubs.la/Q03LThJ00
☁️ Discover how @awscloud is powering a new era of processor design. Join Jeremy Dahan at #RISCVSummit as he explores cloud-first hardware/software co-design and real-world RISC-V innovation. 🔗 Register: events.linuxfoundation.org/riscv-summit/p… #RISCVEverywhere
Researchers at @ucddublin developed a RISC-V SoC that tightly integrates the @nvidia Deep Learning Accelerator (NVDLA) with a streamlined RISC-V core. The key innovation? A bare-metal execution model that leads to faster execution. @electropages ➡️ hubs.la/Q03L-PFz0
RISC-V International CEO Andrea Gallo joined @DanielNenni to discuss how the community is driving RISC-V’s global and industry success, and how that spirit will be on full display at this year’s #RISCVSummit. Listen to the conversation: hubs.la/Q03Mm2Hq0
RISC-V underpins billions of shipped cores, from tiny sensor devices to consumer computer components, right up to HPC. Whether you're just starting your RISC-V journey or looking to shape its global momentum, #RISCVSummit is the best place to be. 👉 hubs.la/Q03L-NC90
Exclusive Discount for RISC-V Summit NA 2025 The RISC-V Summit NA 2025 will take place on October 22-23. DeepComputing is offering a special 10% discount on all products during October 2025! Don't miss out—get yours today! 📍 Learn more: store.deepcomputing.io #framework…
Build custom 64-bit RISC-V Linux images with Yocto! Join Frank Vasquez from Packt for hands-on setup, debugging, and optimization. Limited seats → hubs.la/Q03M41yH0
Discover What’s Next in RISC-V Innovation at ANDES RISC-V CON Munich! Join us for an exclusive afternoon of cutting-edge insights into RISC-V processor and real-world applications 📍 Smartvillage Bogenhausen 🗓 14 October 2025, 13:00-17:00 🔗2vx.io/3yUszSZ
📖 Explore this month’s Featured Work Series: A RISC-V based accelerator for Post Quantum Cryptography: hubs.la/Q03LGqmf0
🔔 Agenda Is Here! Discover what’s coming at 2025 Andes RISC-V CON Munich 🚀 🎯Register: pse.is/84jsgz 📆 Oct 14 | 🕘13:00–17:00 CET | 📍Smartvillage Bogenhausen 🙌Insights, real-world use cases, live demos & RISC-V talks by industry leaders. Don't miss!
Haven’t checked out the #RISCVSummit agenda yet? Now’s the time! See who’s taking the stage and start planning your must-see sessions: hubs.la/Q03LmXyd0 📅 Join us October 22-23!
RISC-V accelerates innovation by enabling the right performance-per-power through ongoing ISA evolution. In a recent discussion with @jonpeddie’s David Harold, RISC-V International's Andrea Gallo explored RISC-V advancements driving progress worldwide: hubs.la/Q03LmKTr0
Join the RISC-V Developer Workshops Oct 22 with experts from @Google, AWS and more. Hands-on hardware + software sessions. Bonus: Workshop registrants get a code to attend Day 2 of #RISCVSummit for just $200. Seats are limited → hubs.la/Q03L9HgS0
At the recent #FMS2025, XCENA announced its first product, MX1 Computational Memory. Made up of “thousands” of in-house RISC-V cores, MX1 offers near-data processing reducing CPU-memory overhead and enabling petabyte-scale SSD backed expansion. hubs.la/Q03LmCkH0
This International Podcast Day, take a moment to explore the voices shaping the future of #RISCV. Explore conversations with industry leaders, innovators, and community members driving the ISA revolution on our news page here: hubs.la/Q03LmsPZ0 #InternationalPodcastDay
Dev. Workshop Spotlight: Learn to Design and Verify a 6-Stage Pipelined RISC-V CPU. Join Rishiyur S. Nikhil, Ph.D., from Bluespec, Inc. for an immersive Hardware Track session at the RISC-V Developer Workshops. Seats are filling fast, register now: hubs.la/Q03L9KJ_0
📢 Are you building with RISC-V? Show your work at @embedded_world 2026! Submit your abstracts by Monday, Sept. 29: embedded-world.de/en/press/press… Excited to see the RISC-V community in action. #RISCVEverywhere #embeddedworld #ew26
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