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2x Baseboards (the final ECOSCALE platform) powered up! 64 FPGAs tightly interconnected & ready to perform acceleration tasks. Each baseboard hosts 8x QFDBs, so the platform gathers 16 QFDBs, with a total of 64 Xilinx Zynq Ultrascale+ MPSoCs and 1 TByte of distributed DDR memory!
The Intel AIB is a die-to-die interconnect standard that speeds development and improves performance. Here’s how it’s promoting chiplet adoption: intel.ly/2HAbjf4
.@DARPA recently unveiled its first SSITH prototype that uses open source @risc_v cores. The program aims to release 15 different prototypes ranging from low-end IoT devices to high-end systems. Check out this article at @TechTarget to learn more: buff.ly/30u3crO
Neural nets for AI are limited by slow processing and their need for extensive computing resources. Now two groups have demoed all-optical neural networks that do all processing with light, making neural nets faster and more energy efficient. #ai buff.ly/32imilj
Congratulations @Appentra! Parallelware Trainer aims to make parallel programming open to everyone... not just ninja programmers😊
MIT Researchers built a 16-bit carbon nanotube-based microprocessor that can execute the full RISC-V instruction set The 14,000-transistor chip executed a classic Hello World program news.mit.edu/2019/carbon-na…
The @upscale_project faces the challenge of demonstrating that #AI can also deal with real industrial simulation models, such as full size vehicles, aerodynamics or crash to enhance the design process of #ElectricVehicles! Discover how 👉bit.ly/2Pdvu8B #WAIC2019 #ML #EVs
ICYMI: Watch 👀 the video of the latest in the monthly #HPC Best Practices Webinar Series from the IDEAS Productivity project for ECP: Software Management Plans in Research Projects. Presenter Shoaib Ahmed Sufi of the Software Sustainability Institute bit.ly/2Z7Ehss
📣📣 @Evolve_H2020 is site of the day at CSS winner 🤗
More on that first trillion-transistor “chip,” from Dr. @hsienhsinlee. sigarch.org/the-first-tril…
sigarch.org
The First Trillion-Transistor Chip: A New Design Space
There was stunning news at the HotChips-31 conference held at Stanford Memorial Auditorium last week. Cerebras, a startup company working on machine learning accelerators in stealth mode, finally c…
August is almost over, so onto some more intricate stuff, instead of #SummerReading 😃 A chapter by EPI authors in the Proceedings of the 5th CESA, An Approach for a Future #Automotive eHPC #Semiconductor Platform @fer_unizg @EB_Automotive @BMWGroup @AtosFR @SpringerNature
(Lucky) Blade #13 has been installed in the HPC rack testbed of @ExaNeSt_H2020 as we are getting ready for our final project review. ExaNeSt.eu
.@AllAboutCircuit spoke with @teodoroj, interim director of the @CHIPSAlliance, to discuss how the Alliance aims to “collaboratively create hardware and open source development tools for the masses.” buff.ly/2YNouzD
The 3-A Intel Enpirion EN6338 PowerSoC is faster, smaller, and more efficient. Learn more in this tutorial: intel.ly/2XU9puX
Google’s New Switching Tech Makes Its Latest Subsea Cable Cheaper, Simpler datacenterknowledge.com/networks/googl…
Great to see that the #ACACES19 poster session made it onto the local Fiuggi 'What's on' board 😅
An industry & program first! Under our 3DSoC program, the first monolithic 3D device structures produced in a fab were unveiled yesterday at our #ERISummit by Dr. Max Shulaker of @MIT. go.usa.gov/xyyGJ
ECP's Center for Efficient Exascale Discretizations helps applications leverage future architectures by developing state-of-the-art discretization algorithms that better exploit the hardware and deliver a performance gain over conventional methods. bit.ly/2xU25EY
You have the power to shape Europe. 10 European citizens’ initiatives have already been registered in 2019! Our Forum is here to help you drive your own initiative to success. Learn more → collab.ec.europa.eu/wiki/eci/ #EUTakeTheInitiative
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