Reyyyansh's profile picture.

Reyansh

@Reyyyansh

Pinned

For years, software devs had LeetCode. But hardware engineers? We were invisible. Until now. ⚡ We just built something the hardware world has been waiting for. Video drops tomorrow. Waitlist LIVE →waitlist.hdlhub.com #HDLHub #MadeInIndia #FPGA #HDL #Verilog

Reyyyansh's tweet image. For years, software devs had LeetCode.

But hardware engineers?

We were invisible.

Until now. ⚡

We just built something the hardware world has been waiting for.

Video drops tomorrow.

 Waitlist LIVE →waitlist.hdlhub.com

#HDLHub #MadeInIndia #FPGA #HDL #Verilog

How many of you have searched for “practice Verilog questions"????


Introducing HDL Hub — the first-ever Verilog & HDL problem-solving platform. Built by Indian 🇮🇳 engineers. For every digital designer on the planet. waitlist.hdlhub.com


Reyansh reposted

should i go dark mode or this looks fine? a full hero section with everything , going to add a footer to it and call it a day for today for frontend


Reyansh reposted

Brand new try , how does it look ?

chokoskoderr's tweet image. Brand new try , how does it look ?

Building something that you may not have realised existed; have you ever considered that hardware can be attacked in the same way that software can? You will get to know. Soon.....

Reyyyansh's tweet image. Building something that you may not have realised existed; have you ever considered that hardware can be attacked in the same way that software can? You will get to know. Soon.....

Can we simulate a ring oscillator without adding a delay? I've been stuck on this since the morning. Anyone is having any idea how to do this in verilog.....


Reyansh reposted

Guys i published my first ever blog on medium , it's on rate limiters and implementing two kinds of such from scratch! link below

chokoskoderr's tweet image. Guys i published my first ever blog on medium , it's on rate limiters and implementing two kinds of such from scratch! 
link below

🚨 Built a custom I²C Master in SystemVerilog from the protocol up. ✅ START/STOP control ✅ 7-bit addressing ✅ R/W ops + ACK/NACK ✅ Open-drain SDA logic ✅ FSM + parameterized timing 🧪 Verified via waveform simulation 🔗 GitHub: github.com/Reyansh17/I2c

Reyyyansh's tweet image. 🚨 Built a custom I²C Master in SystemVerilog from the protocol up.

✅ START/STOP control
✅ 7-bit addressing
✅ R/W ops + ACK/NACK
✅ Open-drain SDA logic
✅ FSM + parameterized timing
🧪 Verified via waveform simulation
🔗 GitHub: github.com/Reyansh17/I2c

Reyansh reposted

Websockets : a classical issue faced when coding in a high level language , you dont have control over EVERYTHING you declare an what goes on under the hood , this is why real programmers love c/c++ and rust has become so popular But this encapsulation is good for beginners! 🧵👇

chokoskoderr's tweet image. Websockets : a classical issue faced when coding in a high level language , you dont have control over EVERYTHING you declare an what goes on under the hood , this is why real programmers love c/c++ and rust has become so popular But this encapsulation is good for beginners!
🧵👇

Going to post a small banger on how sockets dont work with express’ app.listen



Built a FIFO buffer in SystemVerilog! 🔹 16-entry memory 🔹 Push/Pop logic 🔹 Empty/Full flags 🔹 Overrun/Underrun detection 🔹 Threshold alerts 🔹 Simulated in Vivado Code: github.com/Reyansh17/FIFO

Reyyyansh's tweet image. Built a FIFO buffer in SystemVerilog!

🔹 16-entry memory
🔹 Push/Pop logic
🔹 Empty/Full flags
🔹 Overrun/Underrun detection
🔹 Threshold alerts
🔹 Simulated in Vivado

Code: github.com/Reyansh17/FIFO
Reyyyansh's tweet image. Built a FIFO buffer in SystemVerilog!

🔹 16-entry memory
🔹 Push/Pop logic
🔹 Empty/Full flags
🔹 Overrun/Underrun detection
🔹 Threshold alerts
🔹 Simulated in Vivado

Code: github.com/Reyansh17/FIFO

Reyansh reposted

made a basic chat app , plan to add many more features to it!


Reyansh reposted

ok so as i have lost my first thread which i wrote and need to write this again if you see this please do like and repost if you feel like its worth it , Peace thread starts below🧵👇


Reyansh reposted

💔 Not Happy with this #Ceasefire -Who is gonna answer 26 victim families....? -Who gonna answer jawan families, who sacrificed their life in this incomplete w@r? #IndianArmy


Reyansh reposted

Sitting a few km from the Line of Control, I am hearing loud bangs of artillery shells and mortar bombs. Time now is 1942h, more than 2.5 hours after beginning of the cessation of firing announcement. Ganesha Willing, will record the sounds and share later


United States Trends

Loading...

Something went wrong.


Something went wrong.