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#fpga search results

digikey's profile picture. We get technical
DigiKey
@digikey
Apr 4

FPGAs didn’t appear overnight, they’re the result of decades of innovation in digital logic ⚡ Step inside the story👉 bit.ly/4sTqDay #FPGA #innovation #eMagazine With sponsored articles from @Arduino, @ADI_News, @hammondmfg, and @TXInstruments

digikey's tweet image. FPGAs didn’t appear overnight, they’re the result of decades of innovation in digital logic ⚡ Step inside the story👉 bit.ly/4sTqDay #FPGA #innovation #eMagazine With sponsored articles from @Arduino, @ADI_News, @hammondmfg, and @TXInstruments
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controlpaths's profile picture. Full time FPGA designer and DSP enthusiast. Also I write a blog about FPGA and DSP where I share projects and treaks.
Pablo T.
 @controlpaths
Nov 18

As #FPGA developer, last week I worked almost every day with the #Linux Device Tree. ​This must be what they call Full Stack developer...

controlpaths's tweet image. As #FPGA developer, last week I worked almost every day with the #Linux Device Tree. ​This must be what they call Full Stack developer...
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Underfox3's profile picture. Physicist, Telecom Engineering lover, HPC Enthusiast. Prog Rock/Metal fan.
Underfox
 @Underfox3
Jan 14

In this paper is presented a chunked FFT convolution approach enabling 450K length sequence by 450K length filter convolutions on an Alveo U200 FPGA with 2.8 MB BRAM through chunking and overlap-add reconstruction. #FPGA arxiv.org/pdf/2601.06065

Underfox3's tweet image. In this paper is presented a chunked FFT convolution approach enabling 450K length sequence by 450K length filter convolutions on an Alveo U200 FPGA with 2.8 MB BRAM through chunking and overlap-add reconstruction. #FPGA arxiv.org/pdf/2601.06065
Underfox3's tweet image. In this paper is presented a chunked FFT convolution approach enabling 450K length sequence by 450K length filter convolutions on an Alveo U200 FPGA with 2.8 MB BRAM through chunking and overlap-add reconstruction. #FPGA arxiv.org/pdf/2601.06065
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controlpaths's profile picture. Full time FPGA designer and DSP enthusiast. Also I write a blog about FPGA and DSP where I share projects and treaks.
Pablo T.
 @controlpaths
Mar 4

Tomorrow I'll be at #RootedCon talking about how #FPGA are the best option for future #HSM. One of the benefits is that #cryptographic algorithms are designed for HW. In the article I explore how to implement an AES128 using ECB and CTR. Check it out! controlpaths.com/2026/03/01/aes…

controlpaths's tweet card. Step-by-step implementation of AES-128 in Verilog from an ECB core to a practical CTR wrapper, including key expansion, block handling, and simulation with NIST test vectors.
Implementing AES-128 in Verilog: ECB core and CTR wrapper
Source: controlpaths.com
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PlatformIO_Org's profile picture. Make #EmbeddedSystems developers and teams happy!
PlatformIO
 @PlatformIO_Org
Dec 25

#LearnEmbedded 🎓 "FPGA Design for Embedded Systems Specialization" Decode the Secrets of the #FPGA in Embedded Systems. Enhance career opportunities and build better systems by acquiring skills in FPGA design 👉 coursera.org/specialization… 📌 #EmbeddedSystems #Semiconductor

PlatformIO_Org's tweet image. #LearnEmbedded 🎓 "FPGA Design for Embedded Systems Specialization" Decode the Secrets of the #FPGA in Embedded Systems. Enhance career opportunities and build better systems by acquiring skills in FPGA design 👉 coursera.org/specialization… 📌 #EmbeddedSystems #Semiconductor
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digikey's profile picture. We get technical
DigiKey
@digikey
Apr 18

FPGAs didn’t appear overnight, they’re the result of decades of innovation in digital logic ⚡ Revisit the moment that changed everything👉 bit.ly/4sTqDay #FPGA #innovation #eMagazine With sponsored articles from @Arduino, @ADI_News, @hammondmfg and @TXInstruments.

digikey's tweet image. FPGAs didn’t appear overnight, they’re the result of decades of innovation in digital logic ⚡ Revisit the moment that changed everything👉 bit.ly/4sTqDay #FPGA #innovation #eMagazine With sponsored articles from @Arduino, @ADI_News, @hammondmfg and @TXInstruments.
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DSOhnaka's profile picture. FPGAによる画像処理などを行っていま「した」。これから、新しいミュージックシンセサイザーを作ろうと思っています。どんなものかは秘密ですが、ヒントだけ言うと、1万~2万個のオシレータを持つ、FPGAに実装されたハードウェア・アディティブシンセサイザーで、エンベロープコントロールの概念から脱却した「非オルガン」シンセです
大中庸生
@DSOhnaka
Apr 19

当時はいまいち謎めいていたこの現象を、Claudeさんが数学的に説明し、絶賛してくれました。🤩 なんちゅう心強い時代になったことか…💦 #AdditiveSynthesizer #FPGA #Claude

DSOhnaka's tweet image. 当時はいまいち謎めいていたこの現象を、Claudeさんが数学的に説明し、絶賛してくれました。🤩 なんちゅう心強い時代になったことか…💦 #AdditiveSynthesizer #FPGA #Claude
DSOhnaka's tweet image. 当時はいまいち謎めいていたこの現象を、Claudeさんが数学的に説明し、絶賛してくれました。🤩 なんちゅう心強い時代になったことか…💦 #AdditiveSynthesizer #FPGA #Claude
DSOhnaka's profile picture. FPGAによる画像処理などを行っていま「した」。これから、新しいミュージックシンセサイザーを作ろうと思っています。どんなものかは秘密ですが、ヒントだけ言うと、1万~2万個のオシレータを持つ、FPGAに実装されたハードウェア・アディティブシンセサイザーで、エンベロープコントロールの概念から脱却した「非オルガン」シンセです
大中庸生
@DSOhnaka
Nov 14, 2020

とりあえず、2048個のサイン波オシレータを、996Hz～1004Hzの間で約0.004Hz（正確には1/256Hz)刻みでデチューンしたものを全て同一レベル(最大レベルの97%）で鳴らしてミックスダウンすると、この様な予想外の結果になりましたが、そう言われてみればそうなる気がする🤔 #FPGA #ハードシンセ

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DRoca1110's profile picture. RTL & Host-Bypass MEV. Time separates those who wait from those who execute. At sub-microsecond levels, speed is strictly bound by the laws of physics
David Roca
 @DRoca1110
Apr 13

@hadickM Markets don't reward heroics, they reward being right. We just hit 3.10ns RTL reaction on Solana/Arbitrum via SPECTRA V10. Full hardware bypass (Zero-OS/CPU) The TradFi latency moat is evaporating as silicon catches up. Baseline for the new cycle. #Solana #MEV #FPGA

DRoca1110's tweet image. @hadickM Markets don't reward heroics, they reward being right. We just hit 3.10ns RTL reaction on Solana/Arbitrum via SPECTRA V10. Full hardware bypass (Zero-OS/CPU) The TradFi latency moat is evaporating as silicon catches up. Baseline for the new cycle. #Solana #MEV #FPGA
HadickM's profile picture. General Partner at @Dragonfly_xyz | Previously investing and advising at GoldenTree, @GoldmanSachs, and @PJTPartners
Rob Hadick ＞|＜
@HadickM
Apr 12

The discourse this weekend around venture capital, especially in crypto, broadly misses the mark. Venture capital is a marketplace, and venture capitalists sit at the center of it. Most of the conversation has missed how decisions are actually made on both sides. I have clients

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MicrochipTech's profile picture. 8-/16-/32-bit MCUs, analog and Flash-IP solutions. The content in our X feed may include AI-generated imagery, performers and/or audio.
MicrochipTechnologyInc.
@MicrochipTech
Mar 14

From traditional to New Space, designers need scalable qualification paths. RTG4™ FPGAs offer QML-V, QML-Q and RT Mil-Plastic on proven silicon, balancing reliability, cost and performance. Read the blog: mchp.us/4seWdj2. #RadiationTolerant #Space #FPGA

MicrochipTech's tweet image. From traditional to New Space, designers need scalable qualification paths. RTG4™ FPGAs offer QML-V, QML-Q and RT Mil-Plastic on proven silicon, balancing reliability, cost and performance. Read the blog: mchp.us/4seWdj2. #RadiationTolerant #Space #FPGA
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controlpaths's profile picture. Full time FPGA designer and DSP enthusiast. Also I write a blog about FPGA and DSP where I share projects and treaks.
Pablo T.
 @controlpaths
Apr 16

Talking about new #FPGA that landed recently on my desk, look this beautiful board from @iwave_systems It features a powerful Versal ACAP that I am going to use in my next talk. Stay connected!

controlpaths's tweet image. Talking about new #FPGA that landed recently on my desk, look this beautiful board from @iwave_systems It features a powerful Versal ACAP that I am going to use in my next talk. Stay connected!
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MicrochipTech's profile picture. 8-/16-/32-bit MCUs, analog and Flash-IP solutions. The content in our X feed may include AI-generated imagery, performers and/or audio.
MicrochipTechnologyInc.
@MicrochipTech
Apr 10

Attackers exploit weak links. A security mesh removes them by distributing protection across silicon, firmware and interfaces. See how PolarFire® SoC FPGAs build it in from the start. Read the blog: mchp.us/3Qcw1HN. #EmbeddedSecurity #FPGA #SystemDesign

MicrochipTech's tweet image. Attackers exploit weak links. A security mesh removes them by distributing protection across silicon, firmware and interfaces. See how PolarFire® SoC FPGAs build it in from the start. Read the blog: mchp.us/3Qcw1HN. #EmbeddedSecurity #FPGA #SystemDesign
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controlpaths's profile picture. Full time FPGA designer and DSP enthusiast. Also I write a blog about FPGA and DSP where I share projects and treaks.
Pablo T.
 @controlpaths
Jan 27

I love #FPGA hidden gems. Today it's time for the AS02MC04, a Kintex UltraScale+ based board with 2 SFP+. Want to see it in action? I explain how to set up this #NIC in #Vivado to enable full 10Gbps connectivity. controlpaths.com/2026/01/18/as0…

controlpaths's tweet card. Quick notes on bringing up the AS02MC04 Kintex UltraScale+ NIC card: where the clocks come from and how to configure the GTY transceivers for an internal or external loopback test.
AS02MC04 (Alibaba Cloud) Kintex UltraScale+ NIC
Source: controlpaths.com
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MakerIO's profile picture. An electronics project space powered by @DigiKey Come #MakeWithDigiKey!
maker.io
 @MakerIO
Nov 10

Why #FPGA? 🗣️ @ShawnHymel talks about it!

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AmpheoElec's profile picture. Ampheo Electronics: Genuine products, great prices, full-service, partnerships.
AmpheoElectronics
 @AmpheoElec
Apr 13

How to Use FPGA for Image Processing? FPGA image processing is most useful when you need high throughput, low latency, and deterministic timing. Instead of sending every frame to a CPU and waiting for software to process it. Details: ampheo.com/blog/how-to-us… #FPGA #ImageProcessing

AmpheoElec's tweet image. How to Use FPGA for Image Processing? FPGA image processing is most useful when you need high throughput, low latency, and deterministic timing. Instead of sending every frame to a CPU and waiting for software to process it. Details: ampheo.com/blog/how-to-us… #FPGA #ImageProcessing
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PadPoet's profile picture. Games industry pro. Developed & led #communities for @commodoreofcl, @Socialpoint, @505_Games & @PlayStationEU in the past. Fitness addict.
Lucas Liaskos
 @PadPoet
Apr 16

Epic MiSTer update! #MiSTerFPGA #FPGA #StreetFighter

hyp36rmax's profile picture. Expressive. Social Experience. Gamer. PC Builder. Father. Bboy. Gearhead. #urbanCULTURED These opinions are all mine...
F. Eiji Marinas
@hyp36rmax
Apr 16

New kimchiman52 #MisterFPGA 3S-ARM Street Fighter 3rd Strike is out! 2026-04-16 ☑️New video options — H Size, Vertical Crop, Scale modes, and H/V Position controls added to the OSD for fine-tuning the image on your display (works on both analog CRT and HDMI). ☑️Smoother motion

hyp36rmax's tweet card. Peak slop porting. Contribute to kimchiman52/3s-mister-arm development by creating an account on GitHub.
Releases · kimchiman52/3s-mister-arm
Source: github.com
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controlpaths's profile picture. Full time FPGA designer and DSP enthusiast. Also I write a blog about FPGA and DSP where I share projects and treaks.
Pablo T.
 @controlpaths
Dec 24

I hope Santa brings you all the #FPGA dev boards you wished for. If you end up with a microcontroller instead, you’ll know exactly where you stand on the "Naughty or Nice" list. Enjoy the break and get ready for more FPGA articles next year!

controlpaths's tweet image. I hope Santa brings you all the #FPGA dev boards you wished for. If you end up with a microcontroller instead, you’ll know exactly where you stand on the "Naughty or Nice" list. Enjoy the break and get ready for more FPGA articles next year!
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splinedrive's profile picture. BMX rider | Embedded Linux engineer. Open-source silicon: Linux-capable RISC-V SoC (ASIC tape-out, @TinyTapeout / https://t.co/SclO7UyrVv).
asic destroyer
@splinedrive
Feb 23

Built the hardware myself. KianV SoC v2 custom RISC V running on FPGA now booting Linux 7.0 systems engineer touched logic design it escalated :) #riscv #fpga #linux #opensource #kernelv7

splinedrive's tweet image. Built the hardware myself. KianV SoC v2 custom RISC V running on FPGA now booting Linux 7.0 systems engineer touched logic design it escalated :) #riscv #fpga #linux #opensource #kernelv7
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DRoca1110's profile picture. RTL & Host-Bypass MEV. Time separates those who wait from those who execute. At sub-microsecond levels, speed is strictly bound by the laws of physics
David Roca
 @DRoca1110
Apr 16

1.258 Trillion packets processed on Alveo U50. Over 1.6 BILLION Alpha Hits identified with zero drops. ​Bare silicon reality at a scale most can’t even simulate. ​#FPGA #HFT #MEV #U50 #100G #UltraLowLatency

DRoca1110's tweet image. 1.258 Trillion packets processed on Alveo U50. Over 1.6 BILLION Alpha Hits identified with zero drops. ​Bare silicon reality at a scale most can’t even simulate. ​#FPGA #HFT #MEV #U50 #100G #UltraLowLatency
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DRoca1110's profile picture. RTL & Host-Bypass MEV. Time separates those who wait from those who execute. At sub-microsecond levels, speed is strictly bound by the laws of physics
David Roca
 @DRoca1110
4 h

Software in DeFi is an illusion. Here is the physical proof. [+] 500 MHz [+] 18 ns (Tick-to-Trade) [+] 1.25T packets burn-in Intel Agilex > AMD Alveo. NVIDIA BlueField-3, you're next. #FPGA #HFT #LowLatency #QuantTrading #IntelAgilex #NVIDIA #QuantTrading #AMD

DRoca1110's tweet image. Software in DeFi is an illusion. Here is the physical proof. [+] 500 MHz [+] 18 ns (Tick-to-Trade) [+] 1.25T packets burn-in Intel Agilex > AMD Alveo. NVIDIA BlueField-3, you're next. #FPGA #HFT #LowLatency #QuantTrading #IntelAgilex #NVIDIA #QuantTrading #AMD
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SmartUSB's profile picture. USBやシングルボードコンピュータとFPGAを利用した使いやすくて高性能なFPGAボードを開発・販売しています。この製品を核として、FPGA設計、ボード設計、ソフトウエア設計などのデザインサービスも提供しています。
プライムシステムズ
 @SmartUSB
9 h

組み込み向けFPGAボードを探している方へ。 AX-Card7は名刺サイズで装置内に組み込みやすく、I/O電圧も1.2〜3.3Vに対応、混在も可能。 計測・制御・通信など幅広いアプリケーションに実績あり。 長期供給・国内製造で安心の開発環境を提供します。 prime-sys.co.jp/products/axcar…　#smartusb　#FPGA #USB

SmartUSB's tweet card. AX-Card7システム開発ボード高速・広帯域アプリケーションにも対応可能な小型ボード製品名刺サイズだから機器への組み込みも容易です。ロイヤリティーフリーで使えます。さまざまな計測・制御システムに適用事例が多くあります。ハードウエア仕様製品型番と価格AX-Card7/35C2　　　\136,000　　（XC7A35T-2FFG484C搭載モデル）AX-Card7/100C2　　 \154,0...
AX-Card7システム開発ボード | Prime Systems, Inc.
Source: prime-sys.co.jp
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TinaLiu1727872's profile picture. Anna Liu, from Semicon, offers a variety of electronic component. If necessary, kindly contact at info@semicone.com📧
Anna Liu
 @TinaLiu1727872
12 h

EV & FPGA Key Components​ ✅ Authentic & Ready to Ship ◎BQ79616PAPRQ1, TI's ASIL-D compliant 16S battery monitor ◎10M08SAE144I7G, Intel MAX 10 FPGA (8K LEs, 101 I/O) DM for instant quote #FPGA #Electronics 📩 [email protected] 💬 +86 13106942163 🔗 semicone.com

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saihara_fpga's profile picture. 「動くけれど壊れる」設計を減らしたい。 CDC・タイミング・SPI/UARTなど、 FPGA設計でつまずきやすいポイントを実務ベースで解説しています。 FPGA初心者向けの入門書をZennで公開中👇 https://t.co/ivvGPAyudF
S.S｜FPGA設計開発
 @saihara_fpga
14 h

1ビットなら「1クロックの遅れ」で済む同期処理も、バスになると「値の整合性崩壊」という致命的バグに変わります。Valid信号があれば大丈夫、という誤解。なぜそれでは防げないのか。実機で沼にハマる前に知っておきたい、クロック間の落とし穴をまとめました。 #FPGA #Zenn zenn.dev/saihara_dev/ar…

saihara_fpga's tweet card. 【実戦FPGA設計】その2段FF、多ビットでは破綻します ― バス同期の落とし穴
【実戦FPGA設計】その2段FF、多ビットでは破綻します ― バス同期の落とし穴
Source: zenn.dev
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AdrianTonyII's profile picture. Music 🎶 🎵 songwriter and producing music 🎶 🎵 👌 🙌inventor of Eden and Nova
Adrian Tony
@AdrianTonyII
14 h

Nova — Pattern-Based Cognition No symbols No probabilities No neural nets Built on CRU Motifs (Create / Read / Update) Deterministic. Pattern → Pattern only ~1.4 MB No GPU Now seeking hardware collaboration (FPGA / pattern-native architecture) singmypoem.com #FPGA

AdrianTonyII's tweet card. Welcome to Eden Adrian’s 29 current written and produced song list below 🎵 Music for the Soul *Tap to Listen […]
Eden Main
Source: singmypoem.com
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RockycoJL's profile picture. AI for FPGA/ASIC, Algorithm-hardware co-design, MATLAB to HLS
jiejielei
 @RockycoJL
19 h

What if FPGA design ran at software speed? Describe the architecture in a 5-line recipe.json. AI writes the Python golden model, cycle-accurate simulator, Verilog RTL, and cocotb testbench. Zero hand-written RTL. N=1024→8192, 445 MHz, −46% DSP. #FPGA #AI #Verilog

RockycoJL's tweet image. What if FPGA design ran at software speed? Describe the architecture in a 5-line recipe.json. AI writes the Python golden model, cycle-accurate simulator, Verilog RTL, and cocotb testbench. Zero hand-written RTL. N=1024→8192, 445 MHz, −46% DSP. #FPGA #AI #Verilog
RockycoJL's tweet image. What if FPGA design ran at software speed? Describe the architecture in a 5-line recipe.json. AI writes the Python golden model, cycle-accurate simulator, Verilog RTL, and cocotb testbench. Zero hand-written RTL. N=1024→8192, 445 MHz, −46% DSP. #FPGA #AI #Verilog
RockycoJL's tweet image. What if FPGA design ran at software speed? Describe the architecture in a 5-line recipe.json. AI writes the Python golden model, cycle-accurate simulator, Verilog RTL, and cocotb testbench. Zero hand-written RTL. N=1024→8192, 445 MHz, −46% DSP. #FPGA #AI #Verilog
RockycoJL's tweet image. What if FPGA design ran at software speed? Describe the architecture in a 5-line recipe.json. AI writes the Python golden model, cycle-accurate simulator, Verilog RTL, and cocotb testbench. Zero hand-written RTL. N=1024→8192, 445 MHz, −46% DSP. #FPGA #AI #Verilog
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DRoca1110's profile picture. RTL & Host-Bypass MEV. Time separates those who wait from those who execute. At sub-microsecond levels, speed is strictly bound by the laws of physics
David Roca
 @DRoca1110
20 h

If you are building an AppChain to monopolize your protocol value, stop relying on Layer 7 firewalls. The future of DeFi doesn't belong to whoever has the best code; it belongs to whoever controls the gate. #DeFi #AppChains #FPGA #HFT

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DSOhnaka's profile picture. FPGAによる画像処理などを行っていま「した」。これから、新しいミュージックシンセサイザーを作ろうと思っています。どんなものかは秘密ですが、ヒントだけ言うと、1万~2万個のオシレータを持つ、FPGAに実装されたハードウェア・アディティブシンセサイザーで、エンベロープコントロールの概念から脱却した「非オルガン」シンセです
大中庸生
@DSOhnaka
Apr 19

つまり、これが私の犯した大間違い‼️ 「倍音合成」に閉じこもり、「10240ビンを使いきれない…」と悩んでいた【青春時代】の挫折の記録ですわ💦 #AdditiveSynthesizer #FPGA

DSOhnaka's profile picture. FPGAによる画像処理などを行っていま「した」。これから、新しいミュージックシンセサイザーを作ろうと思っています。どんなものかは秘密ですが、ヒントだけ言うと、1万~2万個のオシレータを持つ、FPGAに実装されたハードウェア・アディティブシンセサイザーで、エンベロープコントロールの概念から脱却した「非オルガン」シンセです
大中庸生
@DSOhnaka
Mar 27, 2021

#ハードシンセ #FPGA #AdditiveSynthesizer いつもの環境(ウィーンコンツェルトハウスのモーツアルトホール【擬似】）で倍音構成変えながら鳴らしてみました。 (曲はヴィヴァルディの冬の第3楽章）

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lefinnois's profile picture. Back to Twitter... for now. RédacChef de @hackablemag & @gnulinuxmag - https://t.co/8yrSS6Acij - https://t.co/hw3JoG5ACi
Denis Bodor / @lefinnois.bsky.social
 @lefinnois
Apr 19

Le stream de tout à l'heure est maintenant disponible sur Youtube: youtube.com/watch?v=5DULYe… On continue d'explorer #LITEX et les #FPGA en ajoutant un contrôleur de leds adressables et en le pilotant en C (plus d'autres choses)...

lefinnois's tweet card. LefStream

youtube.com

YouTube

LefStream

Source: youtube.com
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DSOhnaka's profile picture. FPGAによる画像処理などを行っていま「した」。これから、新しいミュージックシンセサイザーを作ろうと思っています。どんなものかは秘密ですが、ヒントだけ言うと、1万~2万個のオシレータを持つ、FPGAに実装されたハードウェア・アディティブシンセサイザーで、エンベロープコントロールの概念から脱却した「非オルガン」シンセです
大中庸生
@DSOhnaka
Apr 19

当時はいまいち謎めいていたこの現象を、Claudeさんが数学的に説明し、絶賛してくれました。🤩 なんちゅう心強い時代になったことか…💦 #AdditiveSynthesizer #FPGA #Claude

DSOhnaka's tweet image. 当時はいまいち謎めいていたこの現象を、Claudeさんが数学的に説明し、絶賛してくれました。🤩 なんちゅう心強い時代になったことか…💦 #AdditiveSynthesizer #FPGA #Claude
DSOhnaka's tweet image. 当時はいまいち謎めいていたこの現象を、Claudeさんが数学的に説明し、絶賛してくれました。🤩 なんちゅう心強い時代になったことか…💦 #AdditiveSynthesizer #FPGA #Claude
DSOhnaka's profile picture. FPGAによる画像処理などを行っていま「した」。これから、新しいミュージックシンセサイザーを作ろうと思っています。どんなものかは秘密ですが、ヒントだけ言うと、1万~2万個のオシレータを持つ、FPGAに実装されたハードウェア・アディティブシンセサイザーで、エンベロープコントロールの概念から脱却した「非オルガン」シンセです
大中庸生
@DSOhnaka
Nov 14, 2020

とりあえず、2048個のサイン波オシレータを、996Hz～1004Hzの間で約0.004Hz（正確には1/256Hz)刻みでデチューンしたものを全て同一レベル(最大レベルの97%）で鳴らしてミックスダウンすると、この様な予想外の結果になりましたが、そう言われてみればそうなる気がする🤔 #FPGA #ハードシンセ

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lefinnois's profile picture. Back to Twitter... for now. RédacChef de @hackablemag & @gnulinuxmag - https://t.co/8yrSS6Acij - https://t.co/hw3JoG5ACi
Denis Bodor / @lefinnois.bsky.social
 @lefinnois
Apr 19

It's #FPGA time (again) ! Le stream démarre dans 5 petite minutes et c'est sur : twitch.tv/lefinnois_

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DSOhnaka's profile picture. FPGAによる画像処理などを行っていま「した」。これから、新しいミュージックシンセサイザーを作ろうと思っています。どんなものかは秘密ですが、ヒントだけ言うと、1万~2万個のオシレータを持つ、FPGAに実装されたハードウェア・アディティブシンセサイザーで、エンベロープコントロールの概念から脱却した「非オルガン」シンセです
大中庸生
@DSOhnaka
Apr 19

Claudeさんによると、AIの発展にも寄与できるんだそうです。そして、暗に「はよやれ…🙃」と急かすような図を…💦 #AdditiveSynthesizer #FPGA

DSOhnaka's tweet image. Claudeさんによると、AIの発展にも寄与できるんだそうです。そして、暗に「はよやれ…🙃」と急かすような図を…💦 #AdditiveSynthesizer #FPGA
DSOhnaka's tweet image. Claudeさんによると、AIの発展にも寄与できるんだそうです。そして、暗に「はよやれ…🙃」と急かすような図を…💦 #AdditiveSynthesizer #FPGA
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digikey's profile picture. We get technical
DigiKey
@digikey
Apr 18

FPGAs didn’t appear overnight, they’re the result of decades of innovation in digital logic ⚡ Revisit the moment that changed everything👉 bit.ly/4sTqDay #FPGA #innovation #eMagazine With sponsored articles from @Arduino, @ADI_News, @hammondmfg and @TXInstruments.

digikey's tweet image. FPGAs didn’t appear overnight, they’re the result of decades of innovation in digital logic ⚡ Revisit the moment that changed everything👉 bit.ly/4sTqDay #FPGA #innovation #eMagazine With sponsored articles from @Arduino, @ADI_News, @hammondmfg and @TXInstruments.
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lefinnois's profile picture. Back to Twitter... for now. RédacChef de @hackablemag & @gnulinuxmag - https://t.co/8yrSS6Acij - https://t.co/hw3JoG5ACi
Denis Bodor / @lefinnois.bsky.social
 @lefinnois
Apr 18

Demain matin 8h, comme tous les dimanches, on parle à nouveau de #FPGA et de #LITEX. Cette fois, on va explorer l'ajout de périphériques dans notre SoC #RISCV avec des petites couleurs toutes mimi qui clignotent ! Et ça se passera ici : twitch.tv/lefinnois_

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ElectronicaAzi's profile picture. Electronica Azi: news and technical articles for the design engineers within research, development and technical management in the electronics field.
Electronica Azi
@ElectronicaAzi
Apr 18

Siemens and NVIDIA enable AI chip verification at trillion-cycle scale using Veloce proFPGA CS, accelerating design validation before silicon. | More info at: international.electronica-azi.ro/siemens-accele… #AI #Semiconductors #FPGA #Verification #NVIDIA #Siemens #ChipDesign #SoC #Electronics #eda

ElectronicaAzi's tweet image. Siemens and NVIDIA enable AI chip verification at trillion-cycle scale using Veloce proFPGA CS, accelerating design validation before silicon. | More info at: international.electronica-azi.ro/siemens-accele… #AI #Semiconductors #FPGA #Verification #NVIDIA #Siemens #ChipDesign #SoC #Electronics #eda
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DRoca1110's profile picture. RTL & Host-Bypass MEV. Time separates those who wait from those who execute. At sub-microsecond levels, speed is strictly bound by the laws of physics
David Roca
 @DRoca1110
Apr 18

Industry says porting HFT cores from Xilinx to Intel takes months. I'm doing it this weekend. SPECTRA Intel Agilex 5. Target: ≥0.000ns slack. Then a 1.258T packet hardware burn-in. Intel vs AMD Alveo cage match. Results Monday. Place your bets. #FPGA #HFT #Intel #AMD

DRoca1110's tweet image. Industry says porting HFT cores from Xilinx to Intel takes months. I'm doing it this weekend. SPECTRA Intel Agilex 5. Target: ≥0.000ns slack. Then a 1.258T packet hardware burn-in. Intel vs AMD Alveo cage match. Results Monday. Place your bets. #FPGA #HFT #Intel #AMD
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Jetstor's profile picture. MD, retrogamer from Brazil - also SNSD Sone, Shenmue, Star Trek, Chuck, Iron Man & Comics fan - welcome!! 🌟👀
Jetstor
 @Jetstor
Apr 17

3DO FPGA Core "Cannot Be Accurate On The MiSTer" Says Creator timeextension.com/news/2026/04/3… #News #MiSTerFPGA #FPGA

Jetstor's tweet image. 3DO FPGA Core "Cannot Be Accurate On The MiSTer" Says Creator timeextension.com/news/2026/04/3… #News #MiSTerFPGA #FPGA
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Obijuan_cube's profile picture. Hola! Soy Obijuan! I'm a researcher on robotics, but I define myself as a hacker. I really believe on the opensource spirit of sharing information. Work at URJC
Juan Gonzalez
 @Obijuan_cube
Apr 17

pero tras este inocente led hay un RISCV RV32I segmentado, con interrupciones y registro de control implementados. Capaz de ejecutar un total de 49 instrucciones diferentes.... Lo que vemos es sólo la punta del Icebereg!!! #FPGA #RISCV #AlhambraII

Obijuan_cube's tweet image. pero tras este inocente led hay un RISCV RV32I segmentado, con interrupciones y registro de control implementados. Capaz de ejecutar un total de 49 instrucciones diferentes.... Lo que vemos es sólo la punta del Icebereg!!! #FPGA #RISCV #AlhambraII
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Obijuan_cube's profile picture. Hola! Soy Obijuan! I'm a researcher on robotics, but I define myself as a hacker. I really believe on the opensource spirit of sharing information. Work at URJC
Juan Gonzalez
 @Obijuan_cube
Apr 17

¡Ya tengo sintezado el procesador HADES-V! Es el RV32I que estamos construyendo en el curso. Este es el ejemplo hola mundo: Encender un LED. ¡Funciona! #riscv #fpga #AlhambraII

Obijuan_cube's tweet image. ¡Ya tengo sintezado el procesador HADES-V! Es el RV32I que estamos construyendo en el curso. Este es el ejemplo hola mundo: Encender un LED. ¡Funciona! #riscv #fpga #AlhambraII
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Obijuan_cube's profile picture. Hola! Soy Obijuan! I'm a researcher on robotics, but I define myself as a hacker. I really believe on the opensource spirit of sharing information. Work at URJC
Juan Gonzalez
 @Obijuan_cube
Apr 17

¡Ya tengo terminado el #RISCV segmentado para el curso del HADES-V! Pasa todos los tests. Ahora es el momento de sintetizarlo para la #AlhambraII. En esta simulación se ve el momento exacto en el que se envía el patrón 0xAA a los LEDs de simulación #FPGA

Obijuan_cube's tweet image. ¡Ya tengo terminado el #RISCV segmentado para el curso del HADES-V! Pasa todos los tests. Ahora es el momento de sintetizarlo para la #AlhambraII. En esta simulación se ve el momento exacto en el que se envía el patrón 0xAA a los LEDs de simulación #FPGA
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lefinnois's profile picture. Back to Twitter... for now. RédacChef de @hackablemag & @gnulinuxmag - https://t.co/8yrSS6Acij - https://t.co/hw3JoG5ACi
Denis Bodor / @lefinnois.bsky.social
 @lefinnois
Apr 5

Victoire \o/ La carte Colorlight a subi sa transplantation de SDRAM avec succès, 8Mio (M12L64322A) -> 32 Mio (IS42S32800) et le mem_test semble positif. Quelques étranges problèmes d'alimentation (ou de bruit) subsistent, WIP donc... #FPGA #LITEX

lefinnois's tweet image. Victoire \o/ La carte Colorlight a subi sa transplantation de SDRAM avec succès, 8Mio (M12L64322A) -> 32 Mio (IS42S32800) et le mem_test semble positif. Quelques étranges problèmes d'alimentation (ou de bruit) subsistent, WIP donc... #FPGA #LITEX
lefinnois's tweet image. Victoire \o/ La carte Colorlight a subi sa transplantation de SDRAM avec succès, 8Mio (M12L64322A) -> 32 Mio (IS42S32800) et le mem_test semble positif. Quelques étranges problèmes d'alimentation (ou de bruit) subsistent, WIP donc... #FPGA #LITEX
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MakerIO's profile picture. An electronics project space powered by @DigiKey Come #MakeWithDigiKey!
maker.io
 @MakerIO
Jan 28, 2025

Discover #FPGA with @ShawnHymel in this 12 episode playlist 📹 Learn: 🍎 ✔️the Basics ✔️clouds & Procedural Assignments ✔️finite State Machines ✔️memory & Block Ram ✔️PLL & Glitches ....and MORE! Get started here 🔽 dky.bz/49w19qC

MakerIO's tweet image. Discover #FPGA with @ShawnHymel in this 12 episode playlist 📹 Learn: 🍎 ✔️the Basics ✔️clouds & Procedural Assignments ✔️finite State Machines ✔️memory & Block Ram ✔️PLL & Glitches ....and MORE! Get started here 🔽 dky.bz/49w19qC
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PlatformIO_Org's profile picture. Make #EmbeddedSystems developers and teams happy!
PlatformIO
 @PlatformIO_Org
Dec 25

#LearnEmbedded 🎓 "FPGA Design for Embedded Systems Specialization" Decode the Secrets of the #FPGA in Embedded Systems. Enhance career opportunities and build better systems by acquiring skills in FPGA design 👉 coursera.org/specialization… 📌 #EmbeddedSystems #Semiconductor

PlatformIO_Org's tweet image. #LearnEmbedded 🎓 "FPGA Design for Embedded Systems Specialization" Decode the Secrets of the #FPGA in Embedded Systems. Enhance career opportunities and build better systems by acquiring skills in FPGA design 👉 coursera.org/specialization… 📌 #EmbeddedSystems #Semiconductor
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hackablemag's profile picture. L'embarqué à sa source ! Tous les deux mois chez votre marchand de journaux, et en ligne sur Connect. Rédac-chef ⇒ @lefinnois
Hackable Magazine
 @hackablemag
Feb 10

#FPGA facile : petite présentation et prise en main de #LiteX avec notre nouvel article offert de la semaine. À découvrir sans plus tarder sur notre base documentaire : connect.ed-diamond.com/hackable/hk-05….

hackablemag's tweet image. #FPGA facile : petite présentation et prise en main de #LiteX avec notre nouvel article offert de la semaine. À découvrir sans plus tarder sur notre base documentaire : connect.ed-diamond.com/hackable/hk-05….
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YLRabbit's profile picture. ⚙️Enthusiastic programmer. ⚔️Love CRPGs, fpga and blinking LEDs. 🌿Villager. 🦖 FreeBSD
YRabbit
 @YLRabbit
Apr 5

The original signal is 2.98 Hz, divided by 2 and then by 5—0.298 Hz, divided by 2 and then by 3.5—0.42571 Hz. #Apicula has learned to divide by all sorts of numbers by combining the CLKDIV2 and CLKDIV primitives🤣 #fpga

YLRabbit's tweet image. The original signal is 2.98 Hz, divided by 2 and then by 5—0.298 Hz, divided by 2 and then by 3.5—0.42571 Hz. #Apicula has learned to divide by all sorts of numbers by combining the CLKDIV2 and CLKDIV primitives🤣 #fpga
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Vicharak_In's profile picture. We make computers that you can use to build robots, drones, intelligent machines, IoT solutions, or simply for fun and experimentation
Vicharak
@Vicharak_In
Apr 3

Built for what’s next. Experience our hardware at Electronica India 2026. Precision. Performance. Possibility. 📍 Booth H11.25 | Hall 11 #EdgeAI #EmbeddedSystems #FPGA #StartupIndia #Innovation #TechLife #OnTheRise #WeAreGrowing

Vicharak_In's tweet image. Built for what’s next. Experience our hardware at Electronica India 2026. Precision. Performance. Possibility. 📍 Booth H11.25 | Hall 11 #EdgeAI #EmbeddedSystems #FPGA #StartupIndia #Innovation #TechLife #OnTheRise #WeAreGrowing
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9000martin9000's profile picture. Guns! Games! Dead Commies! Rebellion to tyrants is obedience to God!
martin
 @9000martin9000
Nov 17

i really need to lose some weight so i went to play golf today. @analogue #fpga #neogeo

9000martin9000's tweet image. i really need to lose some weight so i went to play golf today. @analogue #fpga #neogeo
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regymm0's profile picture. Post-undergrad, FPGA, hardware, osdev. https://t.co/iTO6Xq1QDB :Take my boards home! Delightful in darkness, delicious in dungeon @regymm@mas.to
RegYMM レジム
 @regymm0
Apr 4

What do you use to debug PCIe? Frequent reboots are required, and I use a headless Ryzen 3700X, accessed by SSH, with a static IP address. Can easily hook up 2 or 3 cards, parallel debuggin #Xilinx #FPGA GTP and GTX transceivers!

regymm0's tweet image. What do you use to debug PCIe? Frequent reboots are required, and I use a headless Ryzen 3700X, accessed by SSH, with a static IP address. Can easily hook up 2 or 3 cards, parallel debuggin #Xilinx #FPGA GTP and GTX transceivers!
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wolfSSL's profile picture. The most popular open source, embedded TLS. Active in #IoTSecurity, #Avionics, #Automotive & more. Over 5B connections secured! #TLS13 #SecureYourConnectivity
wolfSSL Embedded SSL/TLS; FIPS 140-3
@wolfSSL
May 9

wolfSSL had an amazing visit to @RadionaOrg! Huge thanks to Goran Mahovlic and the team for the warm welcome and the opportunity to present wolfBoot at the OpenHardware Meet-up. Projects like the #ULX3S #FPGA + #ESP32 are truly inspiring! @crowd_supply @MouserElecEU @MouserElec

wolfSSL's tweet image. wolfSSL had an amazing visit to @RadionaOrg! Huge thanks to Goran Mahovlic and the team for the warm welcome and the opportunity to present wolfBoot at the OpenHardware Meet-up. Projects like the #ULX3S #FPGA + #ESP32 are truly inspiring! @crowd_supply @MouserElecEU @MouserElec
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DutraCGI's profile picture. Cofounder/CTO at UaiLabs // Telecom Engineer Grad. // C++ / Python / FPGA/ GnuRadio // Microwave / SDR / Ham radio 🇧🇷
Paulo Dutra - PU4THZ
 @DutraCGI
Mar 11, 2025

Developing one #16APSK Modulator on #FPGA using #PipelineCHDL ! Testbench Datapath: #LFSR -> APSK16 Map -> #CIC Filter -> out Simulation done with #ghdl + #cocotb, data plotted using #numpy and #matplotlib ! #dsp #sdr #HDL #ccsds #rf #psk #apsk #modem

DutraCGI's tweet image. Developing one #16APSK Modulator on #FPGA using #PipelineCHDL ! Testbench Datapath: #LFSR -> APSK16 Map -> #CIC Filter -> out Simulation done with #ghdl + #cocotb, data plotted using #numpy and #matplotlib ! #dsp #sdr #HDL #ccsds #rf #psk #apsk #modem
DutraCGI's tweet image. Developing one #16APSK Modulator on #FPGA using #PipelineCHDL ! Testbench Datapath: #LFSR -> APSK16 Map -> #CIC Filter -> out Simulation done with #ghdl + #cocotb, data plotted using #numpy and #matplotlib ! #dsp #sdr #HDL #ccsds #rf #psk #apsk #modem
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digikey's profile picture. We get technical
DigiKey
@digikey
Apr 18

FPGAs didn’t appear overnight, they’re the result of decades of innovation in digital logic ⚡ Revisit the moment that changed everything👉 bit.ly/4sTqDay #FPGA #innovation #eMagazine With sponsored articles from @Arduino, @ADI_News, @hammondmfg and @TXInstruments.

digikey's tweet image. FPGAs didn’t appear overnight, they’re the result of decades of innovation in digital logic ⚡ Revisit the moment that changed everything👉 bit.ly/4sTqDay #FPGA #innovation #eMagazine With sponsored articles from @Arduino, @ADI_News, @hammondmfg and @TXInstruments.
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splinedrive's profile picture. BMX rider | Embedded Linux engineer. Open-source silicon: Linux-capable RISC-V SoC (ASIC tape-out, @TinyTapeout / https://t.co/SclO7UyrVv).
asic destroyer
@splinedrive
Feb 23

Built the hardware myself. KianV SoC v2 custom RISC V running on FPGA now booting Linux 7.0 systems engineer touched logic design it escalated :) #riscv #fpga #linux #opensource #kernelv7

splinedrive's tweet image. Built the hardware myself. KianV SoC v2 custom RISC V running on FPGA now booting Linux 7.0 systems engineer touched logic design it escalated :) #riscv #fpga #linux #opensource #kernelv7
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hackablemag's profile picture. L'embarqué à sa source ! Tous les deux mois chez votre marchand de journaux, et en ligne sur Connect. Rédac-chef ⇒ @lefinnois
Hackable Magazine
 @hackablemag
Nov 20

Démarrez en développement #FPGA avec #Python & #LiteX grâce à notre liste de lecture du mois. Rendez-vous sans plus tarder sur connect.ed-diamond.com/liste-de-lectu… pour la découvrir. Bonne lecture !

hackablemag's tweet image. Démarrez en développement #FPGA avec #Python & #LiteX grâce à notre liste de lecture du mois. Rendez-vous sans plus tarder sur connect.ed-diamond.com/liste-de-lectu… pour la découvrir. Bonne lecture !
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embedded_comp's profile picture. The leading source of articles, videos, blogs, podcasts and events for embedded developers #iot #ai #embeddedworld #ew26 @embedded_world @electronicaFair
Embedded Computing Design
@embedded_comp
Mar 9

Join Sundance at @embedded_world Exhibition&Conference! Don’t miss Chris Bowers’ technical session on March 10 at 14:00 for your chance to win a free SMT135‑C. Visit us at Hall 1 / Booth 1‑500 to see the new SMT135‑C Efinix FPGA board store.sundance.com/product/smt135… #fpga

embedded_comp's tweet image. Join Sundance at @embedded_world Exhibition&Conference! Don’t miss Chris Bowers’ technical session on March 10 at 14:00 for your chance to win a free SMT135‑C. Visit us at Hall 1 / Booth 1‑500 to see the new SMT135‑C Efinix FPGA board store.sundance.com/product/smt135… #fpga
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DigilentInc's profile picture. Making engineering and design technologies understandable and accessible to all by providing high-quality, affordable products.
Digilent
@DigilentInc
Feb 19

New from Adiuvo Engineering ✈️ RTL-based environmental logging with: • Cmod S7 • PmodNAV • SPI master in pure RTL • UART @ 921,600 baud • Python visualization Accel, gyro, mag, pressure & temp — no processor required. Read it here: adiuvoengineering.com/post/microzed-… #FPGA #RTL

DigilentInc's tweet image. New from Adiuvo Engineering ✈️ RTL-based environmental logging with: • Cmod S7 • PmodNAV • SPI master in pure RTL • UART @ 921,600 baud • Python visualization Accel, gyro, mag, pressure & temp — no processor required. Read it here: adiuvoengineering.com/post/microzed-… #FPGA #RTL
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DutraCGI's profile picture. Cofounder/CTO at UaiLabs // Telecom Engineer Grad. // C++ / Python / FPGA/ GnuRadio // Microwave / SDR / Ham radio 🇧🇷
Paulo Dutra - PU4THZ
 @DutraCGI
Mar 24, 2025

Made a #GPU for my #RISCV emulator... It works by using some memory mapped registers accessible by the cpu: Vert queue, commit / busy 1) tri list test 2) emulator debug log 3) "host" (riscv) code to draw Next goal is porting the mmio interface to the actual #FPGA desing...

DutraCGI's tweet image. Made a #GPU for my #RISCV emulator... It works by using some memory mapped registers accessible by the cpu: Vert queue, commit / busy 1) tri list test 2) emulator debug log 3) "host" (riscv) code to draw Next goal is porting the mmio interface to the actual #FPGA desing...
DutraCGI's tweet image. Made a #GPU for my #RISCV emulator... It works by using some memory mapped registers accessible by the cpu: Vert queue, commit / busy 1) tri list test 2) emulator debug log 3) "host" (riscv) code to draw Next goal is porting the mmio interface to the actual #FPGA desing...
DutraCGI's tweet image. Made a #GPU for my #RISCV emulator... It works by using some memory mapped registers accessible by the cpu: Vert queue, commit / busy 1) tri list test 2) emulator debug log 3) "host" (riscv) code to draw Next goal is porting the mmio interface to the actual #FPGA desing...
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Dalekamistoso's profile picture. A person that contributes to FPGA/emulator development, retro software/hardware preservation I also make translations/fixes & tools for all I priorly mentioned
𝕮𝖆𝖗𝖑𝖔𝖘 𝕽𝖔𝖒𝖊𝖗𝖔
 @Dalekamistoso
Mar 23

Este sábado se celebró la RU13 de #MSX la afluencia fue menor a la habitualpor motivos laborales de varios habituales pero nos lo pasamos bien aunque se nos olvidó hacer más fotos 😂os pongo algunas de las cosas que pude fotografiar. #FPGA y #flashjacks: youtu.be/bEqtvGuaEW4

Dalekamistoso's tweet image. Este sábado se celebró la RU13 de #MSX la afluencia fue menor a la habitualpor motivos laborales de varios habituales pero nos lo pasamos bien aunque se nos olvidó hacer más fotos 😂os pongo algunas de las cosas que pude fotografiar. #FPGA y #flashjacks: youtu.be/bEqtvGuaEW4
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DutraCGI's profile picture. Cofounder/CTO at UaiLabs // Telecom Engineer Grad. // C++ / Python / FPGA/ GnuRadio // Microwave / SDR / Ham radio 🇧🇷
Paulo Dutra - PU4THZ
 @DutraCGI
Nov 10

Nothing really special but I just built a Zynq bitstream using #OpenSource tools #GenZ ! Reference: github.com/regymm/GenZ/tr… #FPGA #ZYNQ #AMD #XILINX

DutraCGI's tweet image. Nothing really special but I just built a Zynq bitstream using #OpenSource tools #GenZ ! Reference: github.com/regymm/GenZ/tr… #FPGA #ZYNQ #AMD #XILINX
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RemoteSens_MDPI's profile picture. No. 1 #remotesensing #openaccess journal in Remote Sensing Category in #WoS, published by @MDPIOpenAccess; IF 2024 4.1; CiteScore 2024 8.6; #mdpiremotesensing
Remote Sensing MDPI
 @RemoteSens_MDPI
Oct 16

👉👉 1D-CNN-Transformer for #Radar Emitter #Identification and Implemented on #FPGA ✍️ Xiangang Gao et al. 🔗 brnw.ch/21wWFSE

RemoteSens_MDPI's tweet image. 👉👉 1D-CNN-Transformer for #Radar Emitter #Identification and Implemented on #FPGA ✍️ Xiangang Gao et al. 🔗 brnw.ch/21wWFSE
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