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IEEE Microelectronics Design and Test Symposium

@ieee_mdts

IEEE Microelectronics Design & Test Symposium (MDTS)

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Check out our MDTS 2025 program which includes five plenary speakers and three days of incredible presentations! mdts.ieee.org/program-2025/


The 2025 Conference program is now available and it looks like it's going to be a great symposium. Register now to get early bird pricing. Prices increases April 15th! mdts.ieee.org/program-2025/


Hello everyone! Just a quick reminder that the hotel group rate cut-off is May 4, 2025. More information: mdts.ieee.org/ieee-mdts-2025…


Thank you to our 2025 corporate and university sponsors to date. We greatly appreciate your support of our symposium. mdts.ieee.org

ieee_mdts's tweet image. Thank you to our 2025 corporate and university sponsors to date. We greatly appreciate your support of our symposium.

mdts.ieee.org

MDTS is looking to explain our Program Committee. Please email your principal technical interest and background to us to start a conversation. The effort level of a typical PC member is less than an hour each week (on average) and is to review a maximum of 3 submissions a year.


Our fourth plenary speaker is Dr. Samuel Pagliarini, titled "Reverse Engineering and Backdooring Hardware Accelerators for Postquantum Cryptography" Find out more on 2025 program at: mdts.ieee.org/program-2025/


Hotel Reservation information has been posted. Reserve your room at a great rate! mdts.ieee.org


We have announced three of our plenary speakers for MDTS 2025 Moitreyee Mukherjee Roy, Program Director IBM Research Dr. Wenke Weinreich, Fraunhofer Center Nanoelectronic Technologies Dr. Qiaoyan Yu, Professor UNH, Program Director CISE and SaTC mdts.ieee.org/program-2025/


Key Dates Extended Submission Deadline (abstract and full paper): January 13, 2025 Notification of Acceptance: February 16, 2025 Final Paper Submission: April 13, 2025 mdts.ieee.org


Special Session 5 is inviting papers on emerging issues in Hardware and System Security. mdts.ieee.org

ieee_mdts's tweet image. Special Session 5 is inviting papers on emerging issues in Hardware and System Security.

mdts.ieee.org

Important announcement: Extended Submission Deadline (abstract and full paper): January 13, 2025. Call for Papers and Special Sessions information available on our website: mdts.ieee.org


The 34th MDTS will include a poster session to feature work in progress from participants who are interested to present a poster. Authors of accepted papers and extended summaries will also have the opportunity to present a poster in addition to their oral presentation.


MDTS 2025 TPC has announced the opening of Invited Paper Sessions. Interested authors please contact Program Chair Prof. Tian Xia via email at [email protected].

ieee_mdts's tweet image. MDTS 2025 TPC has announced the opening of Invited Paper Sessions. Interested authors please contact Program Chair Prof. Tian Xia via email at txia@uvm.edu.

Papers, tutorials, posters and speakers are solicited in the following topics of interest: Electronic Testing Technologies, DFT, EDA, Yield Analysis and Optimization,Hardware and System Security, Reliability, Analog/Mixed Signal/RF Circuits and more!


The IEEE Microelectronics Design & Test Symposium (MDTS) provides a forum for academia and industry to learn about the latest advances in microelectronics and to share research and design work. The Symposium environment fosters academic-industry collaboration.


Special Session #3 New Design, Test and Packaging Solutions for Wide Bandgap Technologies More updates to come on our website - mdts.ieee.org


Special Session #2 Emerging materials, devices, circuits, and processing for beyond-CMOS nanoelectronics and heterogeneous integration -spintronic, magnetic, optoelectronic -Neuromorphic and memristive devices -phase change, tunnel, ferroelectric, and cold source transistors -Etc


MDTS 2025 Special Session #1 Testing-aware analog/RF, mixed-signal and digital integrated circuit design approaches with emphasis on, but not limited to: -Built-in self-test -Design for test -On-chip calibration -Machine learning based optimizations -Design automation


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