Michael Neuling
@mikeyneuling
Dad, husband, cyclist, geek, OzLaber, @tenstorrent
Was dir gefallen könnte
Watch @jimkxa and Miles Dooley launch our new @tenstorrent Ascalon core and its debut silicon Atlantis.
We officially launched TT-Ascalon™, the highest performance RISC-V CPU platform in the industry, and introduced Open Chiplet Atlas™, the ecosystem defining a truly open standard for chiplet interoperability. Join the Open Hardware Revolution. Catch the TT-Blueprint event…
We officially launched TT-Ascalon™, the highest performance RISC-V CPU platform in the industry, and introduced Open Chiplet Atlas™, the ecosystem defining a truly open standard for chiplet interoperability. Join the Open Hardware Revolution. Catch the TT-Blueprint event…
Australia - hold positions, benefits Lando Japan - hold positions, benefits Lando Hungary - alternate strategy, benefits Lando Monza - correct pitstop error, benefits Lando Singapore - Lando bangs Oscar almost into the wall, hold positions, benefits Lando.
Tenstorrent decided to publish the first benchmark data for Ascalon's RVV implementation using the instruction throughput benchmark of my rvv-bench benchmark suite. <3 camel-cdr.github.io/rvv-bench-resu… Overall, the results look really good so far: #rvv #riscv #simd #tenstorrent
Great analysis of the @tenstorrent Ascalon #RISCV core from @CamelCdr.
Tenstorrent decided to publish the first benchmark data for Ascalon's RVV implementation using the instruction throughput benchmark of my rvv-bench benchmark suite. <3 camel-cdr.github.io/rvv-bench-resu… Overall, the results look really good so far: #rvv #riscv #simd #tenstorrent
Met with @jimkxa Jim Keller, CEO of @Tenstorrent, a pioneer in the field of AI processors. During the meeting, Jim Keller announced Tenstorrent’s intention to establish an office and operations in #Cyprus, 🇨🇾🇺🇸
TT is the only AI startup company offering pcie cards from the website you can buy it now without signing up or signing ndas.
Tenstorrent and the State of AI Hardware Startups open.substack.com/pub/irrational…
Thank you @insane_analyst (Irrational Analyst) for the visit. As he mentions in the article, I invited him to visit. Here at @tenstorrent we are looking for the community to help tell us what’s going right and where we need to improve. Hope you enjoy! open.substack.com/pub/irrational…
Round D closed, $693,000,000 Well done @tenstorrent Many thanks to our investors Lot's to do, let's get to work x.com/tenstorrent/st…
Tenstorrent is announcing that it has closed over $693M in its Series D funding round at a pre-money valuation of $2B. Samsung Securities and AFW Partners led the round, which was oversubscribed due to strong demand from investors. tenstorrent.com/vision/tenstor…
At @tenstorrent we are making progress on upstream support for our #riscv Ascalon core. We've got support in LLVM now and support for qemu is on the way. github.com/llvm/llvm-proj… github.com/alistair23/qem…
@tenstorrent TT-Ascalon-D8 CPU support was merged into LLVM recently as well. github.com/llvm/llvm-proj…
github.com
[RISCV] Add TT-Ascalon-d8 processor by ppenzin · Pull Request #115100 · llvm/llvm-project
Ascalon is an out-of-order CPU core from Tenstorrent. Overview: https://tenstorrent.com/ip/tt-ascalon Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be added in a separate PR.
MIPS P8700 RISC-V CPU Support Posted For LLVM Compiler phoronix.com/news/MIPS-P870…
phoronix.com
MIPS P8700 RISC-V CPU Support Posted For LLVM Compiler
MIPS has begun working on the open-source compiler toolchain support for their P8700 RISC-V based processors
Turns out I was absolutely spamming the shutter out of excitement so here's a landing collage. Cool to see how much the TVC gimbles to pitch the booster back to vertical before lowering onto the tower.
Splashdown confirmed! Congratulations to the entire SpaceX team on an exciting fifth flight test of Starship!
Mechazilla has caught the Super Heavy booster!
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