synflow's profile picture. Making hardware design (integrated circuits/chips/ASICs and FPGAs) simple, fun, and accessible to all developers. Tweets by @matt2xu. #hardwarelesshard

Synflow

@synflow

Making hardware design (integrated circuits/chips/ASICs and FPGAs) simple, fun, and accessible to all developers. Tweets by @matt2xu. #hardwarelesshard

eepurl.com/bK16-L Merry Christmas, may the New Year bring you joy and laughter!


Enjoy our new simulator for the Cx language! #FPGA is made easier eepurl.com/bC0YFD


What's next: a new simulator for Cx eepurl.com/bAEDkL


The first training session on the Synflow framework is scheduled for tomorrow morning eepurl.com/by_mRH


Live webinar/training presented by Nicolas: "Building applications for FPGA with the Synflow framework" eepurl.com/bybRvn


Attend our training on September 8th eepurl.com/bw0Y4j


The latest version of the Synflow framework is now available! eepurl.com/bu8U3P


If you're on Windows, open the certificate manager by executing certmgr.msc and remove the Startcom intermediate certificates


If you see a warning in Chrome about our website being insecure, it may be that your OS uses the SHA-1 version of intermediate certificates


Wow somebody on #YouTube is (really) mad that @matt2xu mentions the flaws of VHDL and Verilog (see the comments): youtube.com/watch?v=frBnuK…

synflow's tweet card. Should I Learn Verilog or VHDL?

youtube.com

YouTube

Should I Learn Verilog or VHDL?


Synflow reposted

3 Ways Untested Biz Plans Are Worse Than a Waste of Time | Entrepreneur goo.gl/bIKHlx #leanstartup

steube's tweet image. 3 Ways Untested Biz Plans Are Worse Than a Waste of Time | Entrepreneur goo.gl/bIKHlx #leanstartup

Technical update - You will need the latest version of Synflow. eepurl.com/btOZ59


How transistors work - and why it's getting more and more difficult to shrink them youtube.com/watch?v=rtI5wR…


Novelties: ngDesign version 0.76 and new IP on the marketplace eepurl.com/brfGJb


We will start a #kickstarter campaign in the coming weeks! eepurl.com/bpqOuj


Updating our Ethernet MAC core to use the experimental "ready" interface. Sending packets now work on the board!


Feature request #112: turn Cx into VHDL/(System?)Verilog and make ngDesign a synthesizer. WAT

synflow's tweet image. Feature request #112: turn Cx into VHDL/(System?)Verilog and make ngDesign a synthesizer. WAT

Synflow reposted

Europe Is Struggling to Foster a Startup Culture on.wsj.com/1FvEGtI


A big change at Synflow, ngDesign is now open source and the business model evolve eepurl.com/bnfxGf


The problem with FPGAs [and how to solve it] news.ycombinator.com/item?id=9530160


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