#apicula search results

yes! ADC - #apicula -syle 🤣 The blue LEDs are service signals (readiness, counters, etc.), while the top two bars represent ADC measurement data, with the least significant bits at the top. #fpga#gowin#sipeed

Classic Wizardry on #sipeed #Tangprimer25k! Just kidding. The frame is a background image, but the maze itself and the strange spherical creature are the work of the @WillFlux 's 2D accelerator! to check the accuracy of #apicula and #nextpnr on the GW5 series of #gowin #fpga

Gee! ADC went through #yosys and #nextpnr! Does it work on hardware? Absolutely not!🤣 #apicula#fpga#gowin#sipeed

Gee! All 64M, which are organised into these two chips with a 16-bit common bus, are written, read and, most importantly, refreshed normally. I can only use 22 bits for direct addressing, so all this goodness is organised as 16 pages of 4M each.🤣 #apicula#fpga#sipeed#gowin

#Apicula has learned how to form the correct BSRAM initialisation format for the GW5A series!🤣 The @WillFlux 's #isle second chapter is up and running! #fpga#gowin#sipeed

The ims shows the streams after #Apicula and after IDE. The two CRC bytes before the long sequence 1 do not match. This means that I either did not take something into account, took something extra, or did not initialise the the CRC calculation correctly🤪 #fpga#gowin

Gee! 🤣 The GW5 series has very fun PLLs—each can generate 7 different freqs at the outputs. The question: why do you need as many as 6 suchPLLs? :) Well, anyway, #apicula can generate all 7 outputs and distribute them across the clock spines as long as it can :) #fpga#gowin

yep. Cleaning up the crutches turned out to be faster than I expected - PLL VGA #apicula edition :) A perfectly clear square border :)

News about GW5 series - PLL went through #yosys, #nextpnr, and #apicula and started working!🍾 At the moment, there are a huge number of crutches, which I plan to remove in the near future and make the appropriate PR.😉 #fpga#gowin#sipeed

#Apicula acquired its first generator for the GW5 series - OSCA. In this case, its fixed frequency of 200 MHz is divided by 100 (set in the primitive parameter) and then clocks the DFF, resulting in 1 MHz. #gowin #sipeed #fpga

#riscv on #sipeed Tangprimer25k without * LUTRAM and BSRAM, but capable of running simple programs and featuring UART! Thanks to Mecrisp's ** help, it has been shown that even the twisted clock system, modified ALUs, and specific additional DFFs are implemented in #apicula w/o

Added LUT RAM to #apicula for the GW5A series. Hmm... this doesn't seem to resemble prime numbers. Well, it didn't work right away, so there must be some subtleties involved — will investigate🤣 #gowin #sipeed #fpga

Great! The 6th and 7th flip-flops are successfully deployed, complying with control network restrictions, and are working in hardware! Now #apicula can use all 8 flip-flops in the GW5A series cell #gowin #fpga😜

Gee! #apicula has learned how to use dedicated clock pins directly (well, not exactly directly in this series, but it is possible via HCLK)!🍾 🤣 Now I want to deal with the two “extra” flip-flops. #fpga #apicula #sipeed #gowin

Gee! #apicula has learned to use the internal clock generator (well, not entirely internal, it is still external to the chip, but soldered permanently to the #TangPrimer25k board).😜 We are slowly but surely moving towards decent support for the GW5 series of #gowin #fpga!😀

Gee! the clock network of gw5a is working, i.e. spines, taps, and branches cover all four quadrants, and DFFs are working, by the way! 😁 #fpga #apicula#gowin

I come across some blocks in the route whose purpose is unclear, possibly energy-saving switches.🤔 It's fun. #apicula

GW5 family (#TangPrimer25k) got support for huge LUTs in #apicula!🍾 #fpga#sipeed#gowin

M.2 USB SSD wakes up using #ZFS and #FreeBSD. I'll leave that question for later (although I have SATA mechanical drives and it would be annoying to see wake-up failures). I need the Linux command line to create #apicula bases. Qemu works here, which is welcome. But 10 times

@splinedrive 's #riscv thing is running Linux on #tangnano20k . 🤣 But that's not the news, the news is that this is the work of a new #apicula that will allow support for the cool GW5A series #fpga!

That's 27 MHz alright, just as advertised. #tangnano9k #nextpnr #apicula #amaranth

Gee! ADC went through #yosys and #nextpnr! Does it work on hardware? Absolutely not!🤣 #apicula#fpga#gowin#sipeed

Gee! 🤣 The GW5 series has very fun PLLs—each can generate 7 different freqs at the outputs. The question: why do you need as many as 6 suchPLLs? :) Well, anyway, #apicula can generate all 7 outputs and distribute them across the clock spines as long as it can :) #fpga#gowin

Gee! All 64M, which are organised into these two chips with a 16-bit common bus, are written, read and, most importantly, refreshed normally. I can only use 22 bits for direct addressing, so all this goodness is organised as 16 pages of 4M each.🤣 #apicula#fpga#sipeed#gowin

@splinedrive 's #riscv thing is running Linux on #tangnano20k . 🤣 But that's not the news, the news is that this is the work of a new #apicula that will allow support for the cool GW5A series #fpga!

GW5 family (#TangPrimer25k) got support for huge LUTs in #apicula!🍾 #fpga#sipeed#gowin

As usual, the first launch is Terror that flaps in the night. Well something is clearly dividing by something:) #apicula #fpga

Gee, today I have not only segments, but also specific wires and gate wires to reach them. Now the fun part is to do the routing from the network source to each segment, and from the segments horizontally to the sinks. #apicula #fpga

Pulling all my #fpga s out of the drawer. Well, let's get to total testing of the additions to #apicula and #nextpnr 🤣

No skips - significant all wires are routed correctly and all dividers are working properly, division ratio changes.😜 #fpga #apicula #gowin

Routes are being laid out for segmented networks... and ... I don't like it. It's not pretty. I'm going to throw this out the window and rewrite it differently tomorrow. 🤪 #apicula #fpga

#Apicula acquired its first generator for the GW5 series - OSCA. In this case, its fixed frequency of 200 MHz is divided by 100 (set in the primitive parameter) and then clocks the DFF, resulting in 1 MHz. #gowin #sipeed #fpga

#nextpnr reports one DLLDLY out of four engaged! Today's task is getting them to actually work😜 #fpga #apicula #gowin

Great! The 6th and 7th flip-flops are successfully deployed, complying with control network restrictions, and are working in hardware! Now #apicula can use all 8 flip-flops in the GW5A series cell #gowin #fpga😜

Gee! #apicula learned how to feed frequency to PLL input from CLKDIV2 frequency divider!😜 The difficulty was that the CLKDIV2 is not capable of feeding a signal to GP wires and special wires for HF clocks had to be dealt with. (show this is very difficult btw)🤣 #fpga #gowin

So CLKDIV/DIV/2 for all supported chips by #apicula pointless program on #verilog, but since all primitive pins are connected to IO, this prevents the compiler from optimising them and allows me to track which wires go where.😜 #fpga

Well it didn't take me three days to find this missing wire that was preventing CLKDIV from functioning on #Tangnano4k . Just like a detective:) Too bad I didn't make it to February, but I got it to work on GW1N-1, GW1NZ-1, GW1NSR-4C. Only two boards left. #apicula #fpga

News about GW5 series - PLL went through #yosys, #nextpnr, and #apicula and started working!🍾 At the moment, there are a huge number of crutches, which I plan to remove in the near future and make the appropriate PR.😉 #fpga#gowin#sipeed

Well now my soul is almost at peace - the DLLDLY delay mechanism in #gowin chips turned out to be a little bit more complicated than my yesterday's assumptions, but today I got a nice signal shift graph.😉 #fpga #apicula