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HDL Coder

@HDLCoder

13게시물 1팔로워 0팔로우 중
HDLCoder's profile picture.
HDL Coder
 @HDLCoder
2011. 7. 1.

Multiple-clock mode can mix domains in an unfortunate way when clock phases are requested, such as a downsample with phase offsets.

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HDL Coder
 @HDLCoder
2011. 6. 29.

When is a timing controller not a timing controller? When it's a wire! What's worse? When there are two of them!

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HDL Coder
 @HDLCoder
2011. 1. 1.

Capture the moment; carry the day! -D.F.

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HDL Coder
 @HDLCoder
2010. 10. 4.

Look out FPGAs!

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HDL Coder
 @HDLCoder
2010. 7. 19.

Back to the future with Verilog sensitivity lists!

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HDL Coder
 @HDLCoder
2009. 12. 21.

Researching RS cores--get 'em while they're hot!

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HDL Coder
 @HDLCoder
2009. 7. 31.

Bug found in Unit Delay for active-low reset in Verilog

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HDL Coder
 @HDLCoder
2009. 6. 11.

Plan review is done!

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HDL Coder
 @HDLCoder
2009. 5. 28.

Writing code, analyzing code, hope it works!

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HDL Coder
 @HDLCoder
2009. 5. 6.

Test Drive again

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HDL Coder
 @HDLCoder
2009. 5. 6.

Testing again and again and again

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HDL Coder
 @HDLCoder
2009. 5. 6.

Second try from another source

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HDL Coder
 @HDLCoder
2009. 5. 5.

Testing out Twitter for the first time

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