PDVLcc's profile picture. PDVL is an aspect oriented and transaction level Programming, Design and Verification Language. Free & #OS HW\SW #SystemVerilog #Verilog #VHDL #UVM #SVA #PSL

PDVL

@PDVLcc

PDVL is an aspect oriented and transaction level Programming, Design and Verification Language. Free & #OS HW\SW #SystemVerilog #Verilog #VHDL #UVM #SVA #PSL

It'll be interesting how you tackle it. Best wishes and good luck.

Hey guys! Check out my very first blog on Mor1kx formal. Here is it's link harshitha172000.github.io/blog1 @stffrdhrn @gsoc @FossiFoundation



Open access papers till June for "The Fourth ACM SIGPLAN History of Programming Languages Conference, Co-Vital with PLDI 2012": hopl4.sigplan.org dl.acm.org/toc/pacmpl/202…


Inspiring open accessible 2-pager available for LATTE ’21 (Workshop on Languages, Tools, and Techniques for Accelerator Design): capra.cs.cornell.edu/latte21/


PDVL reposted

Trying to count electrons (or holes if I can detect some) as they fly by (almost) at the speed of light. Cycle accurate power consumption measurements of #RISCV cores. Oh boy, it’s not going to work. Wish me luck.

arduissimo's tweet image. Trying to count electrons (or holes if I can detect some) as they fly by (almost) at the speed of light. Cycle accurate power consumption measurements of #RISCV cores. Oh boy, it’s not going to work. Wish me luck.

PDVL reposted

“Test-Case Reduction via Test-Case Generation: Insights From the Hypothesis Reducer” – @DRMacIver, @afd_icl. #ecoop20 #research #paper ➡️ 2020.ecoop.org/details/ecoop-…

ECOOPconf's tweet image. “Test-Case Reduction via Test-Case Generation: Insights From the Hypothesis Reducer” – @DRMacIver, @afd_icl. #ecoop20 #research #paper
➡️  2020.ecoop.org/details/ecoop-…

The best free introductory course on formal verification I have ever seen: intrologic.stanford.edu/public/index.p…


PDVL reposted

The Coq Workshop 2020 will be held online on July 5-6. Everyone is welcome to join! Please see this Discourse post for more detail: coq.discourse.group/t/call-for-par…


PDVL reposted

The REMS-@deep_spec workshop (part of @PLDI 2020) will be held online on June 15-16th: pldi20.sigplan.org/home/rems-deep… Registration is free but it closes on June 5th!


PDVL reposted

Kilocore ? LOL. Kilothreads is the new threat in town ! 64 CUBE-V cores on a KCU116 => 1024 dynamically interleaved threads => ~30 GIPS (Giga Instructions Per Seconds) ! #RISCV

arduissimo's tweet image. Kilocore ? LOL. Kilothreads is the new threat in town ! 64 CUBE-V cores on a KCU116 => 1024 dynamically interleaved threads => ~30 GIPS (Giga Instructions Per Seconds) ! #RISCV

Is doxygen (still) the preferred tool for C++ project documentation? Thanks for your thought. I'm preparing an open source release for my PDVL to SystemVerilog converter tool written in C++. Need to add documentation for it.


Wow that's something. Though I'm not a fan of the language itself, obviously. bluespec.com/2020/01/06/blu…


PDVL reposted

It is with great pleasure to announce the release of the open source Arduissimo project on github. Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programs on the ARTY board (XC7A35T). #riscv #shp #cubev github.com/cloudxcc/Ardui…

arduissimo's tweet image. It is with great pleasure to announce the release of the open source Arduissimo project on github.

Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programs on the ARTY board (XC7A35T). 

#riscv #shp #cubev

github.com/cloudxcc/Ardui…

2nd WOSET Workshop on Open-Source EDA - Breakfast Bytes - Cadence Blogs - Cadence Community shar.es/a37Jd7


PDVL reposted

We would like to invite you to contribute to #abz2020's case study. We welcome submissions that use any formalism (not just ASM, Alloy, B, TLA, VDM and Z). For more information visit abz2020.uni-ulm.de/case-study #abz2020

ABZ_Conference's tweet image. We would like to invite you to contribute to #abz2020's case study. We welcome submissions that use any formalism (not just ASM, Alloy, B, TLA, VDM and Z). For more information visit abz2020.uni-ulm.de/case-study #abz2020

PDVL reposted

And now at full speed! 64 continuously blinky threads on a RISC-V (RV32iMC) based Quad-Core MP-SoC (16 interleaved threads each core) on the ARTY FPGA board. Reaching ~620 MIPS. #threatening #SHP #riscv


The program for the 30th International Workshop on Rapid System Prototyping (RSP) is out. Looking forward to a great week in NY. conferences.telecom-bretagne.eu/rsp-symposium/…


PDVL reposted

Software defined protocols (SDP). Here I2C on a single, interleaved multithreaded RISC-V (RV32iMC). Chain of 8 masters and 8 slaves. Maximal number of active threads = 13. Easy to initialize. #riscv Using system hyper pipelining technique. #SHP

arduissimo's tweet image. Software defined protocols (SDP). Here I2C on a single, interleaved multithreaded RISC-V (RV32iMC). Chain of 8 masters and 8 slaves. Maximal number of active threads = 13. Easy to initialize. #riscv Using system hyper pipelining technique. #SHP

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