Dougall
@dougallj
he/they | mastodon: http://mastodon.social/@dougall / @[email protected]
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Not news, but: Fediverse (active): mastodon.social/@dougall / @dougall@mastodon.social Bluesky: dougall.bsky.social
In celebration JPEG XL being reconsidered for inclusion in Chrome, I created the first ever JPEG XL image which displays its own MD5 hash! $ md5sum hashquine.jxl c0dec0007b5246f7428936d9bed2f446 This website does not render JPEG XL yet, so see the links below
Here it is! Die shot of Apple's A19 SoC🔥🔬 chipwise.tech/our-portfolio/…
very sad that cohost is going. maybe its unique genre of posting, the css crime, will go with it. well, i'm glad that there's this worthy goodbye to it cohost.org/rebane2001/pos…
After 27 years of providing in-depth coverage of the amazing world of PC and mobile hardware, AnandTech is saying farewell. We want to thank everyone from the AnandTech community for their support and passion for what we’ve done over the years anandtech.com/show/21542/end…
CRC checksum is not a cryptographic hash function. It is easy to add a few bytes of garbage at the end of a file so that the CRC of the entire file becomes a desired value. But did you need to do that in the linker? Yes. github.com/rui314/mold/bl…
Analysis of the M4 by @techinsightsinc „key design choice in the Apple M4 is the use of TSMC's high-performance standard cell library for CPU1“ …“UHD libraries for GPU and CPU2“ aka TSMC FinFlex CPU1: P-Cores CPU2: E-Cores techinsights.com/blog/introduci…
Intel is now essentially following Apple's design philosophy, with an integrated memory architecture, a large front-end, a large L1 cache, removal of SMT, 4+4 cores
"Vulkan 1.3 on the M1 in 1 month", by Alyssa Rosenzweig rosenzweig.io/blog/vk13-on-t…
With Lisa's keynote over, I will casually drop this to confirm that y-cruncher v0.8.5 will get #Zen5 optimizations with it's big and fat #AVX512. Release date still ETA - pending final silicon. x.com/Mysticial/stat… ST and BBP will be where the light shines the brightest.
y-cruncher's BBP digit extractor will turn into a proper benchmark for v0.8.5. It's a pure SIMD/AVX workload that doesn't touch memory. Why? The CPU/memory perf gap is becoming so large that the classic Pi benchmarks are turning into pure memory tests. numberworld.org/y-cruncher/new…
FWIW, I've also given it a decent write-up at corsix.org/content/abusin…. Only notable change is putting maskz on the shuffle rather than on the permutexvar, as uops.info suggests maskz costs a few cycles, so might as well put it on the cheaper of the two instructions.
Fantastical deep information about optimizing for Apple Silicon can now be found here: developer.apple.com/download/apple…
Example of why power draw is a poor proxy for how well a program is utilizing your hardware (i7-7700K CPU in this case). In one case, execution port use is heavy and IPC is high, so the CPU's pipeline is running at high utilization. However power draw is low. Second case...
New blog post: "Entropy decoding in Oodle Data: x86-64 6-stream Huffman decoders" fgiesen.wordpress.com/2023/10/29/ent…
Here is @Qualcomm #Oryon single threaded performance: 👉 VS Apple M2: 14% faster at 30% less power 👉 VS Intel i9-13980HK: 1% faster at 70% less power
oh my god
hmm did the guy famous for baselessly accusing someone he didn’t like of being a “pedo guy” just suspend @JUNlPER after she did the same to him?
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