its_matt_h's profile picture. Engineer. Cambridge, UK to San Francisco, US.

Matt Hollands

@its_matt_h

Engineer. Cambridge, UK to San Francisco, US.

Trying to decide whether to use my final 2x STM32L4s for my first prototype or instead use some of my STM32F0s knowing that I will probably need an M4 down the line and I can buy neither chip in the foreseeable future either way. It's like the trolley problem for chips.


Working on an acoustic phase array simulator inspired by @bitluni's videos


Rendered my first #blender project following the @andrewpprice tutorial


I think I caught the ISS on Friday night with some long exposures over Clear Lake, California

its_matt_h's tweet image. I think I caught the ISS on Friday night with some long exposures over Clear Lake, California
its_matt_h's tweet image. I think I caught the ISS on Friday night with some long exposures over Clear Lake, California
its_matt_h's tweet image. I think I caught the ISS on Friday night with some long exposures over Clear Lake, California
its_matt_h's tweet image. I think I caught the ISS on Friday night with some long exposures over Clear Lake, California

I thought I'd finally found reason to put a chip at 45˚, but no, it's still an inferior orientation

its_matt_h's tweet image. I thought I'd finally found reason to put a chip at 45˚, but no, it's still an inferior orientation

Waiting on parts so why not do some mechanical design

its_matt_h's tweet image. Waiting on parts so why not do some mechanical design

Chose an STM32 model for a new design last weekend based on DigiKey having 1000+ in stock - finished the design today and they're all sold out🤦‍♂️Should've pulled the trigger last week


Even using @oshpark's 6 layer service, I find myself most limited by no blind/buried vias and no via in pad when having to miniaturise a design. There just isn't space between components. Still need to optimise the placement before serious routing can begin.

its_matt_h's tweet image. Even using @oshpark's 6 layer service, I find myself most limited by no blind/buried vias and no via in pad when having to miniaturise a design. There just isn't space between components. Still need to optimise the placement before serious routing can begin.

Schrodinger's part @digikey. This doesn't make the component shortage any easier.

its_matt_h's tweet image. Schrodinger's part @digikey. This doesn't make the component shortage any easier.
its_matt_h's tweet image. Schrodinger's part @digikey. This doesn't make the component shortage any easier.

Spent hours debugging an oscillating opamp - turned out to be the LDO was unstable😩


Enjoy a video of the magnetic field when two attracting magnets meet - simulated using FEMM


Got 2kg of 3mm black PLA filament by accident (wanted 1.75mm). If anyone in San Francisco wants it, let me know. Don't want to throw it away.


Loading...

Something went wrong.


Something went wrong.