zipcpu's profile picture. FPGA design engineer and blogger, placing particular emphasis on test and formal verification

Zip CPU

@zipcpu

FPGA design engineer and blogger, placing particular emphasis on test and formal verification

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Wow, lots of new twitter followers just joined. Welcome! Just to give you an opportunity to get to know me and the ZipCPU blog, here's a bit about me and what you can expect here: zipcpu.com/blog/2018/10/0… Again, welcome!


How bad can clock muxing get? This is just two of six mux trees. Notice the wide clock muxes as well. Those are actually mux trees. Ugly? Wait 'till it needs to meet timing.

zipcpu's tweet image. How bad can clock muxing get?  This is just two of six mux trees.  Notice the wide clock muxes as well.  Those are actually mux trees.

Ugly?  Wait 'till it needs to meet timing.

ASIC designers need to worry about clock gates, yes. The ASIC design I'm currently working with is having struggles with clock muxes--don't forget those as well. A second design on my desk has ... way too many muxed clocks for a simple IO controller. I like things simpler.

ASIC designers need to worry about clock gating while FPGA designers just hit compile crazy world out there



Zip CPU reposted

get into FPGAs. they’re not as hyped as AI or robotics, but they’re the hidden backbone of both. you want speed? determinism? ultra-low latency? hardware-level parallelism? that’s FPGA territory. every serious system; autonomous vehicles, defense tech, high-frequency trading,…

oprydai's tweet image. get into FPGAs.

they’re not as hyped as AI or robotics, but they’re the hidden backbone of both.

you want speed? determinism? ultra-low latency? hardware-level parallelism? 
that’s FPGA territory.

every serious system; autonomous vehicles, defense tech, high-frequency trading,…

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