#fpga search results

Usually we don't realize that having a #microprocessor running #Linux, with a direct interface to an #FPGA is probably the most important achievement in decades for #embedded systems. From my point of view.


New Video! - The Analogue 3D Review - Was this FPGA N64 console worth the wait? Watch Here : youtu.be/4rUF8vkL6_U #Analogue3D #N64 #FPGA

ModernVintageG's tweet image. New Video! - The Analogue 3D Review - Was this FPGA N64 console worth the wait? 

Watch Here : youtu.be/4rUF8vkL6_U 

#Analogue3D #N64 #FPGA

Accelerate next-generation medical imaging innovation with our PolarFire® FPGAs—combining certified functional safety, hardware-level security and real-time, low-power AI processing. Read the blog: mchp.us/3JhFmeu. #MedicalImaging #FPGA #FunctionalSafety

MicrochipTech's tweet image. Accelerate next-generation medical imaging innovation with our PolarFire® FPGAs—combining certified functional safety, hardware-level security and real-time, low-power AI processing. Read the blog: mchp.us/3JhFmeu. #MedicalImaging #FPGA #FunctionalSafety

#FPGA Showdown Here's mine! Also just a part of them, maybe one third. Digilent boards are the prettiest in my collection.

regymm0's tweet image. #FPGA Showdown
Here's mine! Also just a part of them, maybe one third. 
Digilent boards are the prettiest in my collection.

How do I challenge you to an FPGA Showdown?

FPGA_Zealot's tweet image. How do I challenge you to an FPGA Showdown?


yes! ADC - #apicula -syle 🤣 The blue LEDs are service signals (readiness, counters, etc.), while the top two bars represent ADC measurement data, with the least significant bits at the top. #fpga#gowin#sipeed


Do you remember your first serious PCB design? Mine is this #Zynq 7010 4-layer board without DDR. The moment of #FPGA JTAG detection will be forever remembered, together with the rusty table, still air, and glorious, responsibility-free days.

regymm0's tweet image. Do you remember your first serious PCB design? 
Mine is this #Zynq 7010 4-layer board without DDR. The moment of #FPGA JTAG detection will be forever remembered, together with the rusty table, still air, and glorious, responsibility-free days.
regymm0's tweet image. Do you remember your first serious PCB design? 
Mine is this #Zynq 7010 4-layer board without DDR. The moment of #FPGA JTAG detection will be forever remembered, together with the rusty table, still air, and glorious, responsibility-free days.

Just got @Vicharak_In 's Shrike-lite. Designed in "ગરવી" Gujarat and Manufactured in India! Will tinker with it in coming months! It's my first FPGA board and will definitely need some steep learning! #FPGA #india #engineering #embedded #mcu

sunilshahu's tweet image. Just got @Vicharak_In 's Shrike-lite. Designed in "ગરવી" Gujarat and Manufactured in India!

Will tinker with it in coming months! It's my first FPGA board and will definitely need some steep learning! 

#FPGA #india #engineering #embedded #mcu
sunilshahu's tweet image. Just got @Vicharak_In 's Shrike-lite. Designed in "ગરવી" Gujarat and Manufactured in India!

Will tinker with it in coming months! It's my first FPGA board and will definitely need some steep learning! 

#FPGA #india #engineering #embedded #mcu

#FPGA developer with open-source toolchains! -> The table -> The screen -> The code (fasm, assembly for FPGA) The lesson is good HDMI output requires SKEW to be FAST, and some more insidious settings that are automatically set by Vivado.

regymm0's tweet image. #FPGA developer with open-source toolchains! 
-> The table
-> The screen
-> The code (fasm, assembly for FPGA)
The lesson is good HDMI output requires SKEW to be FAST, and some more insidious settings that are automatically set by Vivado.
regymm0's tweet image. #FPGA developer with open-source toolchains! 
-> The table
-> The screen
-> The code (fasm, assembly for FPGA)
The lesson is good HDMI output requires SKEW to be FAST, and some more insidious settings that are automatically set by Vivado.
regymm0's tweet image. #FPGA developer with open-source toolchains! 
-> The table
-> The screen
-> The code (fasm, assembly for FPGA)
The lesson is good HDMI output requires SKEW to be FAST, and some more insidious settings that are automatically set by Vivado.

Why #FPGA? 🗣️ @ShawnHymel talks about it!


As #FPGA developer, last week I worked almost every day with the #Linux Device Tree. ​This must be what they call Full Stack developer...

controlpaths's tweet image. As #FPGA developer, last week I worked almost every day with the #Linux Device Tree.

​This must be what they call Full Stack developer...

First of all, a huge thanks to @Vicharak_In and @AksharVastarpar for bringing this beauty into our hands! Just received my Shrike-Lite and I’m super excited to push the limits of my imagination with it! In the coming days, I’ll be posting my experiments... #ShrikeLite #FPGA

Maverick4004's tweet image. First of all, a huge thanks to @Vicharak_In and @AksharVastarpar for bringing this beauty into our hands! 
Just received my Shrike-Lite and I’m super excited to push the limits of my imagination with it!  In the coming days, I’ll be posting my experiments...
#ShrikeLite #FPGA

Seeking ideas for a new #Tang #FPGA board! What would you use a $49 FPGA board with 35K LUTs and 512Mbit DDR4 and MIPI DSI/CSI for? Let us know your project ideas!

SipeedIO's tweet image. Seeking ideas for a new #Tang #FPGA board!
What would you use a $49 FPGA board with 35K LUTs and 512Mbit DDR4 and MIPI DSI/CSI for?
Let us know your project ideas!

FPGAトレーニングコースを開催中🤖 参加者が実装したLチカ(LEDチカチカ)、みてるだけでも楽しい〜✨ #名古屋大学 #ハードウェア #FPGA

KMINagoyaU's tweet image. FPGAトレーニングコースを開催中🤖
参加者が実装したLチカ(LEDチカチカ)、みてるだけでも楽しい〜✨

#名古屋大学 #ハードウェア #FPGA
KMINagoyaU's tweet image. FPGAトレーニングコースを開催中🤖
参加者が実装したLチカ(LEDチカチカ)、みてるだけでも楽しい〜✨

#名古屋大学 #ハードウェア #FPGA

First light! 🔥 ao486 boots DOS on the #TangConsole 138K. HDD, VGA, BIOS, and VGA BIOS are all up and running — watching it hit the DOS prompt on real hardware is surreal. #FPGA #RetroComputing 🎥👇


Amazing example of what GOWIN’s GW5AT FPGA can do — single-chip USB3 implementation keeping performance high and cost low 🔥 #FPGA #Engineering

So, @SipeedIO sent me their new SLogic16U3 USB3 logic analyzer to review(free, no obligation). Inside is just a tiny Gowin GW5AT-LV15 FPGA doing softcore USB3(!!!), which is how they made it so cheap. 800MHz@4ch is quite impressive. My verdict? Definitely going in the tool box.

Spirit532_'s tweet image. So, @SipeedIO sent me their new SLogic16U3 USB3 logic analyzer to review(free, no obligation). Inside is just a tiny Gowin GW5AT-LV15 FPGA doing softcore USB3(!!!), which is how they made it so cheap. 800MHz@4ch is quite impressive. My verdict? Definitely going in the tool box.
Spirit532_'s tweet image. So, @SipeedIO sent me their new SLogic16U3 USB3 logic analyzer to review(free, no obligation). Inside is just a tiny Gowin GW5AT-LV15 FPGA doing softcore USB3(!!!), which is how they made it so cheap. 800MHz@4ch is quite impressive. My verdict? Definitely going in the tool box.
Spirit532_'s tweet image. So, @SipeedIO sent me their new SLogic16U3 USB3 logic analyzer to review(free, no obligation). Inside is just a tiny Gowin GW5AT-LV15 FPGA doing softcore USB3(!!!), which is how they made it so cheap. 800MHz@4ch is quite impressive. My verdict? Definitely going in the tool box.
Spirit532_'s tweet image. So, @SipeedIO sent me their new SLogic16U3 USB3 logic analyzer to review(free, no obligation). Inside is just a tiny Gowin GW5AT-LV15 FPGA doing softcore USB3(!!!), which is how they made it so cheap. 800MHz@4ch is quite impressive. My verdict? Definitely going in the tool box.


#fpga are great, but it's snowed and I need to clear all the paths and the driveway.🙂 (I'm not going to clear my local fir tree, it looks so beautiful in the snow.)

YLRabbit's tweet image. #fpga are great, but it's snowed and I need to clear all the paths and the driveway.🙂 

(I'm not going to clear my local fir tree, it looks so beautiful in the snow.)

Новое видео на канале Школа синтеза цифровых схем: Занятие 1 (2025-26): Введение в маршрут проектирования и упражнения с комбинационной логикой. youtu.be/WxSy26MfwK8 #xilinx #vivado #fpga #плис

ExpertEda's tweet image. Новое видео на канале Школа синтеза цифровых схем: Занятие 1 (2025-26): Введение в маршрут проектирования и упражнения с комбинационной логикой.
youtu.be/WxSy26MfwK8
#xilinx  #vivado #fpga #плис

🚀 The FPGA Market is set to soar from $8.7B in 2025 to $18.6B by 2035 at a 7.2% CAGR! Rising demand for AI, edge computing, 5G, automotive & healthcare solutions is driving growth. 🌐 For more visit:shorturl.at/f3BD2 #FPGA #Semiconductors #AIHardware #EdgeComputing #5G

omrglobal's tweet image. 🚀 The FPGA Market is set to soar from $8.7B in 2025 to $18.6B by 2035 at a 7.2% CAGR! Rising demand for AI, edge computing, 5G, automotive & healthcare solutions is driving growth. 🌐

For more visit:shorturl.at/f3BD2

#FPGA #Semiconductors #AIHardware #EdgeComputing #5G

AumRaj is seeking experienced VLSI engineers to join our team and work on industry driven semiconductor design challenges. No salary bar for the right candidates. Apply Now 📧 [email protected] 📞 +91-7043303488 #aumraj #rtl #fpga #vlsi #iot #asic #design #verification

AumrajInc's tweet image. AumRaj is seeking experienced VLSI engineers to join our team and work on industry driven semiconductor design challenges. No salary bar for the right candidates.

Apply Now
📧 falguni.thakkar@aumraj.com
📞 +91-7043303488

#aumraj #rtl #fpga #vlsi #iot #asic #design #verification

An #FPGA, when incorporated into an #SDR, is incredibly powerful—these systems can provide the needed input/output bandwidth and #processing capabilities for implementing #multi-gigasample rates and #giaghertz-range bandwidths. bit.ly/3vvyjYu


Infineon Technologies has confirmed that AMD successfully tested its 64 Mb HYPERRAM memory and HYPERRAM controller IP with the AMD Spartan UltraScale+ FPGA SCU35 Evaluation Kit. newelectronics.co.uk/content/news/a… #FPGA #MemoryTech #Infineon


🔧 AMD Spartan UltraScale+ SCU35 Kit ya disponible ⚙️ Incluye FPGA SU35P, bajo consumo y alta E/S 🧠 Compatible con Vivado y Vitis 💰 Desde 229$ (~198€), disponible globalmente #FanáticosDelHardware #AMD #FPGA #Hardware fanaticosdelhardware.com/amd-lanza-el-k…


Someday it will be interesting to look at the minimum requirements for the RISCV version of #NetBSD — maybe it will fit into Tangnano20k #fpga?🤪


AGLN250V2-VQG100I #Microchip IC FPGA 68 I/O 100VQFP Find electronic components? Visit our website to get the best quote • 100% Original & New • No MOQ • 365 Days Warranty Email: [email protected] #FPGA #embedded_ic #hardfindelec

_hardfind's tweet image. AGLN250V2-VQG100I #Microchip
IC FPGA 68 I/O 100VQFP
Find electronic components? Visit our website to get the best quote
• 100% Original & New
• No MOQ
• 365 Days Warranty
Email: bubbles@hardfindelectronics.com
#FPGA #embedded_ic #hardfindelec
_hardfind's tweet image. AGLN250V2-VQG100I #Microchip
IC FPGA 68 I/O 100VQFP
Find electronic components? Visit our website to get the best quote
• 100% Original & New
• No MOQ
• 365 Days Warranty
Email: bubbles@hardfindelectronics.com
#FPGA #embedded_ic #hardfindelec

🚨 #SPS25 starts tomorrow! See Lattice’s advanced #FPGA hardware and software solutions for #Industrial and #edgeAI applications at the @EtherCAT_Group, #EXOR, and #Macnica booths.

latticesemi's tweet image. 🚨 #SPS25 starts tomorrow! See Lattice’s advanced #FPGA hardware and software solutions for #Industrial and #edgeAI applications at the @EtherCAT_Group, #EXOR, and #Macnica booths.

Here's a quick demo of 🏝️ Isle.Computer text mode featuring Basic Latin and Block Elements. #FPGA

WillFlux's tweet image. Here's a quick demo of 🏝️ Isle.Computer text mode featuring Basic Latin and Block Elements. #FPGA

Xilinx Alveo U250 is recommended for advanced FPGAs and includes proprietary VHDL code alongside the algorithm. Getting that code is unheard of. #FPGA #Xilinx


#FPGA Showdown Here's mine! Also just a part of them, maybe one third. Digilent boards are the prettiest in my collection.

regymm0's tweet image. #FPGA Showdown
Here's mine! Also just a part of them, maybe one third. 
Digilent boards are the prettiest in my collection.

How do I challenge you to an FPGA Showdown?

FPGA_Zealot's tweet image. How do I challenge you to an FPGA Showdown?


#fpga are great, but it's snowed and I need to clear all the paths and the driveway.🙂 (I'm not going to clear my local fir tree, it looks so beautiful in the snow.)

YLRabbit's tweet image. #fpga are great, but it's snowed and I need to clear all the paths and the driveway.🙂 

(I'm not going to clear my local fir tree, it looks so beautiful in the snow.)

Accelerate next-generation medical imaging innovation with our PolarFire® FPGAs—combining certified functional safety, hardware-level security and real-time, low-power AI processing. Read the blog: mchp.us/3JhFmeu. #MedicalImaging #FPGA #FunctionalSafety

MicrochipTech's tweet image. Accelerate next-generation medical imaging innovation with our PolarFire® FPGAs—combining certified functional safety, hardware-level security and real-time, low-power AI processing. Read the blog: mchp.us/3JhFmeu. #MedicalImaging #FPGA #FunctionalSafety

FPGAトレーニングコースを開催中🤖 参加者が実装したLチカ(LEDチカチカ)、みてるだけでも楽しい〜✨ #名古屋大学 #ハードウェア #FPGA

KMINagoyaU's tweet image. FPGAトレーニングコースを開催中🤖
参加者が実装したLチカ(LEDチカチカ)、みてるだけでも楽しい〜✨

#名古屋大学 #ハードウェア #FPGA
KMINagoyaU's tweet image. FPGAトレーニングコースを開催中🤖
参加者が実装したLチカ(LEDチカチカ)、みてるだけでも楽しい〜✨

#名古屋大学 #ハードウェア #FPGA

First of all, a huge thanks to @Vicharak_In and @AksharVastarpar for bringing this beauty into our hands! Just received my Shrike-Lite and I’m super excited to push the limits of my imagination with it! In the coming days, I’ll be posting my experiments... #ShrikeLite #FPGA

Maverick4004's tweet image. First of all, a huge thanks to @Vicharak_In and @AksharVastarpar for bringing this beauty into our hands! 
Just received my Shrike-Lite and I’m super excited to push the limits of my imagination with it!  In the coming days, I’ll be posting my experiments...
#ShrikeLite #FPGA

Do you remember your first serious PCB design? Mine is this #Zynq 7010 4-layer board without DDR. The moment of #FPGA JTAG detection will be forever remembered, together with the rusty table, still air, and glorious, responsibility-free days.

regymm0's tweet image. Do you remember your first serious PCB design? 
Mine is this #Zynq 7010 4-layer board without DDR. The moment of #FPGA JTAG detection will be forever remembered, together with the rusty table, still air, and glorious, responsibility-free days.
regymm0's tweet image. Do you remember your first serious PCB design? 
Mine is this #Zynq 7010 4-layer board without DDR. The moment of #FPGA JTAG detection will be forever remembered, together with the rusty table, still air, and glorious, responsibility-free days.

Developing one #16APSK Modulator on #FPGA using #PipelineCHDL ! Testbench Datapath: #LFSR -> APSK16 Map -> #CIC Filter -> out Simulation done with #ghdl + #cocotb, data plotted using #numpy and #matplotlib ! #dsp #sdr #HDL #ccsds #rf #psk #apsk #modem

DutraCGI's tweet image. Developing one #16APSK Modulator on #FPGA using #PipelineCHDL ! 

Testbench Datapath:
#LFSR -> APSK16 Map -> #CIC Filter -> out

Simulation done with #ghdl + #cocotb, data plotted using #numpy and #matplotlib !

#dsp #sdr #HDL #ccsds #rf #psk #apsk #modem
DutraCGI's tweet image. Developing one #16APSK Modulator on #FPGA using #PipelineCHDL ! 

Testbench Datapath:
#LFSR -> APSK16 Map -> #CIC Filter -> out

Simulation done with #ghdl + #cocotb, data plotted using #numpy and #matplotlib !

#dsp #sdr #HDL #ccsds #rf #psk #apsk #modem

A new contender takes on the Analogue Pocket 👇 #GameBub #FPGA #RetroHandhelds

retro_dodo's tweet image. A new contender takes on the Analogue Pocket 👇

#GameBub #FPGA #RetroHandhelds

Day 77: ✅ Focused on timing closure and resource balance in TPG pipelines to keep II = 1 at 250 MHz ✅ Obtained partial simulation results for my new paper 📊 ✅ 45 minutes workout 🏋🏻‍♀️ #MachineLearning #AI #FPGA #100DaysofCode

m0b1nai's tweet image. Day 77:

✅ Focused on timing closure and resource balance in TPG pipelines to keep II = 1 at 250 MHz 
✅ Obtained partial simulation results for my new paper 📊
✅ 45 minutes workout 🏋🏻‍♀️

#MachineLearning #AI  #FPGA #100DaysofCode
m0b1nai's tweet image. Day 77:

✅ Focused on timing closure and resource balance in TPG pipelines to keep II = 1 at 250 MHz 
✅ Obtained partial simulation results for my new paper 📊
✅ 45 minutes workout 🏋🏻‍♀️

#MachineLearning #AI  #FPGA #100DaysofCode
m0b1nai's tweet image. Day 77:

✅ Focused on timing closure and resource balance in TPG pipelines to keep II = 1 at 250 MHz 
✅ Obtained partial simulation results for my new paper 📊
✅ 45 minutes workout 🏋🏻‍♀️

#MachineLearning #AI  #FPGA #100DaysofCode

🎃 No tricks, just treats! 🍬 Discover how Lattice provides innovative, low power #FPGA solutions for datacenters, automation/robotics, AI, security, and more: bit.ly/3VO8ldI

latticesemi's tweet image. 🎃 No tricks, just treats! 🍬 Discover how Lattice provides innovative, low power #FPGA solutions for datacenters, automation/robotics, AI, security, and more: bit.ly/3VO8ldI

#FPGA developer with open-source toolchains! -> The table -> The screen -> The code (fasm, assembly for FPGA) The lesson is good HDMI output requires SKEW to be FAST, and some more insidious settings that are automatically set by Vivado.

regymm0's tweet image. #FPGA developer with open-source toolchains! 
-> The table
-> The screen
-> The code (fasm, assembly for FPGA)
The lesson is good HDMI output requires SKEW to be FAST, and some more insidious settings that are automatically set by Vivado.
regymm0's tweet image. #FPGA developer with open-source toolchains! 
-> The table
-> The screen
-> The code (fasm, assembly for FPGA)
The lesson is good HDMI output requires SKEW to be FAST, and some more insidious settings that are automatically set by Vivado.
regymm0's tweet image. #FPGA developer with open-source toolchains! 
-> The table
-> The screen
-> The code (fasm, assembly for FPGA)
The lesson is good HDMI output requires SKEW to be FAST, and some more insidious settings that are automatically set by Vivado.

And now I regret not getting a 32-bit logic analyser.🤣 Remember – 8 inputs are laughable if you're seriously interested in #fpga, get something more powerful right away. SDRAM signal graphs, if anything.😜

YLRabbit's tweet image. And now I regret not getting a 32-bit logic analyser.🤣 

Remember – 8 inputs are laughable if you're seriously interested in #fpga, get something more powerful right away.

SDRAM signal graphs, if anything.😜

Seeking ideas for a new #Tang #FPGA board! What would you use a $49 FPGA board with 35K LUTs and 512Mbit DDR4 and MIPI DSI/CSI for? Let us know your project ideas!

SipeedIO's tweet image. Seeking ideas for a new #Tang #FPGA board!
What would you use a $49 FPGA board with 35K LUTs and 512Mbit DDR4 and MIPI DSI/CSI for?
Let us know your project ideas!

Finally stopped being lazy and configured the analog output on my MiSTer #FPGA

SneedPlays's tweet image. Finally stopped being lazy and configured the analog output on my MiSTer #FPGA

After a whole day talking about #FPGA, it's time for a relaxing evening playing with this new tiny FPGA board based on an @efinixinc Trion FPGA.

controlpaths's tweet image. After a whole day talking about #FPGA, it's time for a relaxing evening playing with this new tiny FPGA board based on an @efinixinc Trion FPGA.

M64 vs #MiSTer – Could ModRetro’s #FPGA #N64 Become the True Successor? Thanks to @timeextension64 for pointing this out. Read it here: metalgamesolid.com/fpga/other-fpg…

MetGsolid's tweet image. M64 vs #MiSTer – Could ModRetro’s #FPGA #N64 Become the True Successor? 
Thanks to @timeextension64 for pointing this out.

Read it here: metalgamesolid.com/fpga/other-fpg…

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