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#spinalhdl search results

Benathon's profile picture. Dev. Founder. Free Speech. #gamedev Bitcoin, XMR. 3D printing. 250mm drones. Linux, C++, RF and DSP with SDR, Verilog, node, WASM. Hackathons. Bay Area.
Benathon
 @Benathon
Feb 26

#SpinalHDL is SOO op, I just need to learn it all #FPGA

Benathon's tweet image. #SpinalHDL is SOO op, I just need to learn it all #FPGA
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pulp_platform's profile picture. A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13.
PULP Platform
 @pulp_platform
Jun 14, 2019

Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH

pulp_platform's tweet image. Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH
pulp_platform's tweet image. Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH
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antmicro's profile picture. Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.
Antmicro
 @antmicro
Feb 28, 2019

See @antmicro’s very own #opensource Zynq Video Board running a #LiteX generated @RISC_V softCPU written in #SpinalHDL, with MIPI CSI-2 camera input and HDMI output, running @ZephyrIoT #RTOS in an example of our open source IP core flow @mithro @enjoy_digital

antmicro's tweet image. See @antmicro’s very own #opensource Zynq Video Board running a #LiteX generated @RISC_V softCPU written in #SpinalHDL, with MIPI CSI-2 camera input and HDMI output, running @ZephyrIoT #RTOS in an example of our open source IP core flow @mithro @enjoy_digital
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ABOpenLtd's profile picture. Helping to build mutually beneficial relationships between technology companies and technical communities.
AB Open
 @ABOpenLtd
Dec 10, 2018

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL

ABOpenLtd's tweet image. Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL
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Rolf_Drechsler's profile picture. Professor for Computer Architecture (@agra_uni_bremen) at @UniBremen. Dean. Director at @DFKI, Head of the Cyber-Physical Systems Group, @noerdman, @truscova
Rolf Drechsler
 @Rolf_Drechsler
Feb 3, 2021

#DATE2021 - Sallar Ahmadi-Pour presenting at the University Booth on "MicroRV32: A #SpinalHDL based #RISC-V Implementation for #FPGAs" @agra_uni_bremen @DFKI #VerSys #scale4edge @BMBF_Bund @DateConference #DATEconference @risc_v #riscv

Rolf_Drechsler's tweet image. #DATE2021 - Sallar Ahmadi-Pour presenting at the University Booth on "MicroRV32: A #SpinalHDL based #RISC-V Implementation for #FPGAs" @agra_uni_bremen @DFKI #VerSys #scale4edge @BMBF_Bund @DateConference #DATEconference @risc_v #riscv
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Daniel_Grosse's profile picture. Professor for Complex Systems at @jkulinz. Interested in #EDA, #Verification, #FormalMethods, #RISCV, #VirtualPrototype, #SystemC.
Daniel Große
 @Daniel_Grosse
May 24, 2022

You are interested in #fuzzing your #SpinalHDL design? Than have a look at "SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs" presented by Katharina Ruep tomorrow at European Test Symposium 2022. 👉 ics.jku.at/files/2022ETS_…

Daniel_Grosse's tweet image. You are interested in #fuzzing your #SpinalHDL design? Than have a look at "SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs" presented by Katharina Ruep tomorrow at European Test Symposium 2022. 👉 ics.jku.at/files/2022ETS_…
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leaflabs's profile picture. Research and engineering services firm focused on low level computing. We love hard problems and elegant solutions.
LeafLabs
 @leaflabs
Dec 9, 2022

Don't miss LeafLabs' Jeff Ciesielski presenting at the #SpinalHDL "Explore the SpinalHDL Landscape" webinar next Friday, December 16. He will be sharing how we're leveraging SpinalHDL to enable the rapid development of devices used for Neuroscience research!

leaflabs's tweet image. Don't miss LeafLabs' Jeff Ciesielski presenting at the #SpinalHDL "Explore the SpinalHDL Landscape" webinar next Friday, December 16. He will be sharing how we're leveraging SpinalHDL to enable the rapid development of devices used for Neuroscience research!
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AdrianByszuk's profile picture. Electronics engineer and hardcore open source enthusiast. I love Linux, FPGA, hard problems and new ideas.
Adrian Byszuk
 @AdrianByszuk
Dec 10, 2018

#SpinalHDL looks like a really powerful language with great code generation performance.

ABOpenLtd's profile picture. Helping to build mutually beneficial relationships between technology companies and technical communities.
AB Open
 @ABOpenLtd
Dec 10, 2018

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL

ABOpenLtd's tweet image. Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL
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masterq_mogumog's profile picture. I moved to Mastodon.
I moved to Mastodon.
 @masterq_mogumog
Jul 22, 2017

SpinalHDLで書かれたFPGA向けRISC-Vプロセッサらしい / “GitHub - SpinalHDL/VexRiscv: A FPGA frien…” htn.to/NnkAkiV #spinalhDL #fpga #risc-v #hdl #cpu

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mostlymoss's profile picture. Are we allowed to be this close? 🏳️‍🌈
Thorsten Knoll
 @mostlymoss
Dec 29, 2016

SpinalHDL-Workshop at 33C3, today, 21:30, Hall C.3. events.ccc.de/congress/2016/… #SpinalHDL #33c3

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SpinalHDL's profile picture.
SpinalHDL
 @SpinalHDL
May 31, 2016

New #SpinalHDL documentation : spinalhdl.github.io/SpinalDoc Help yourself : Try it for your next #FPGA #ASIC project instead of #VHDL #Verilog

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Benathon's profile picture. Dev. Founder. Free Speech. #gamedev Bitcoin, XMR. 3D printing. 250mm drones. Linux, C++, RF and DSP with SDR, Verilog, node, WASM. Hackathons. Bay Area.
Benathon
 @Benathon
Feb 26

#SpinalHDL is SOO op, I just need to learn it all #FPGA

Benathon's tweet image. #SpinalHDL is SOO op, I just need to learn it all #FPGA
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leaflabs's profile picture. Research and engineering services firm focused on low level computing. We love hard problems and elegant solutions.
LeafLabs
 @leaflabs
Dec 9, 2022

Don't miss LeafLabs' Jeff Ciesielski presenting at the #SpinalHDL "Explore the SpinalHDL Landscape" webinar next Friday, December 16. He will be sharing how we're leveraging SpinalHDL to enable the rapid development of devices used for Neuroscience research!

leaflabs's tweet image. Don't miss LeafLabs' Jeff Ciesielski presenting at the #SpinalHDL "Explore the SpinalHDL Landscape" webinar next Friday, December 16. He will be sharing how we're leveraging SpinalHDL to enable the rapid development of devices used for Neuroscience research!
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Daniel_Grosse's profile picture. Professor for Complex Systems at @jkulinz. Interested in #EDA, #Verification, #FormalMethods, #RISCV, #VirtualPrototype, #SystemC.
Daniel Große
 @Daniel_Grosse
May 24, 2022

You are interested in #fuzzing your #SpinalHDL design? Than have a look at "SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs" presented by Katharina Ruep tomorrow at European Test Symposium 2022. 👉 ics.jku.at/files/2022ETS_…

Daniel_Grosse's tweet image. You are interested in #fuzzing your #SpinalHDL design? Than have a look at "SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs" presented by Katharina Ruep tomorrow at European Test Symposium 2022. 👉 ics.jku.at/files/2022ETS_…
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Rolf_Drechsler's profile picture. Professor for Computer Architecture (@agra_uni_bremen) at @UniBremen. Dean. Director at @DFKI, Head of the Cyber-Physical Systems Group, @noerdman, @truscova
Rolf Drechsler
 @Rolf_Drechsler
Feb 3, 2021

#DATE2021 - Sallar Ahmadi-Pour presenting at the University Booth on "MicroRV32: A #SpinalHDL based #RISC-V Implementation for #FPGAs" @agra_uni_bremen @DFKI #VerSys #scale4edge @BMBF_Bund @DateConference #DATEconference @risc_v #riscv

Rolf_Drechsler's tweet image. #DATE2021 - Sallar Ahmadi-Pour presenting at the University Booth on "MicroRV32: A #SpinalHDL based #RISC-V Implementation for #FPGAs" @agra_uni_bremen @DFKI #VerSys #scale4edge @BMBF_Bund @DateConference #DATEconference @risc_v #riscv
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pulp_platform's profile picture. A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13.
PULP Platform
 @pulp_platform
Jun 14, 2019

Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH

pulp_platform's tweet image. Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH
pulp_platform's tweet image. Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH
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antmicro's profile picture. Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.
Antmicro
 @antmicro
Feb 28, 2019

See @antmicro’s very own #opensource Zynq Video Board running a #LiteX generated @RISC_V softCPU written in #SpinalHDL, with MIPI CSI-2 camera input and HDMI output, running @ZephyrIoT #RTOS in an example of our open source IP core flow @mithro @enjoy_digital

antmicro's tweet image. See @antmicro’s very own #opensource Zynq Video Board running a #LiteX generated @RISC_V softCPU written in #SpinalHDL, with MIPI CSI-2 camera input and HDMI output, running @ZephyrIoT #RTOS in an example of our open source IP core flow @mithro @enjoy_digital
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AdrianByszuk's profile picture. Electronics engineer and hardcore open source enthusiast. I love Linux, FPGA, hard problems and new ideas.
Adrian Byszuk
 @AdrianByszuk
Dec 10, 2018

#SpinalHDL looks like a really powerful language with great code generation performance.

ABOpenLtd's profile picture. Helping to build mutually beneficial relationships between technology companies and technical communities.
AB Open
 @ABOpenLtd
Dec 10, 2018

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL

ABOpenLtd's tweet image. Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL
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ABOpenLtd's profile picture. Helping to build mutually beneficial relationships between technology companies and technical communities.
AB Open
 @ABOpenLtd
Dec 10, 2018

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL

ABOpenLtd's tweet image. Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL
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masterq_mogumog's profile picture. I moved to Mastodon.
I moved to Mastodon.
 @masterq_mogumog
Jul 22, 2017

SpinalHDLで書かれたFPGA向けRISC-Vプロセッサらしい / “GitHub - SpinalHDL/VexRiscv: A FPGA frien…” htn.to/NnkAkiV #spinalhDL #fpga #risc-v #hdl #cpu

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mostlymoss's profile picture. Are we allowed to be this close? 🏳️‍🌈
Thorsten Knoll
 @mostlymoss
Dec 29, 2016

SpinalHDL-Workshop at 33C3, today, 21:30, Hall C.3. events.ccc.de/congress/2016/… #SpinalHDL #33c3

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SpinalHDL's profile picture.
SpinalHDL
 @SpinalHDL
May 31, 2016

New #SpinalHDL documentation : spinalhdl.github.io/SpinalDoc Help yourself : Try it for your next #FPGA #ASIC project instead of #VHDL #Verilog

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ABOpenLtd's profile picture. Helping to build mutually beneficial relationships between technology companies and technical communities.
AB Open
 @ABOpenLtd
Dec 10, 2018

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL

ABOpenLtd's tweet image. Tom Verbeure on the VexRiscV CPU: “A New Way to Design”. abopen.com/news/tom-verbe… #FOSSi #RISCV #SpinalHDL
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8
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antmicro's profile picture. Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.
Antmicro
 @antmicro
Feb 28, 2019

See @antmicro’s very own #opensource Zynq Video Board running a #LiteX generated @RISC_V softCPU written in #SpinalHDL, with MIPI CSI-2 camera input and HDMI output, running @ZephyrIoT #RTOS in an example of our open source IP core flow @mithro @enjoy_digital

antmicro's tweet image. See @antmicro’s very own #opensource Zynq Video Board running a #LiteX generated @RISC_V softCPU written in #SpinalHDL, with MIPI CSI-2 camera input and HDMI output, running @ZephyrIoT #RTOS in an example of our open source IP core flow @mithro @enjoy_digital
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Benathon's profile picture. Dev. Founder. Free Speech. #gamedev Bitcoin, XMR. 3D printing. 250mm drones. Linux, C++, RF and DSP with SDR, Verilog, node, WASM. Hackathons. Bay Area.
Benathon
 @Benathon
Feb 26

#SpinalHDL is SOO op, I just need to learn it all #FPGA

Benathon's tweet image. #SpinalHDL is SOO op, I just need to learn it all #FPGA
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0
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pulp_platform's profile picture. A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13.
PULP Platform
 @pulp_platform
Jun 14, 2019

Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH

pulp_platform's tweet image. Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH
pulp_platform's tweet image. Charles Papon presented new methodologies and paradigms emerging from #SpinalHDL. #WOSH
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Rolf_Drechsler's profile picture. Professor for Computer Architecture (@agra_uni_bremen) at @UniBremen. Dean. Director at @DFKI, Head of the Cyber-Physical Systems Group, @noerdman, @truscova
Rolf Drechsler
 @Rolf_Drechsler
Feb 3, 2021

#DATE2021 - Sallar Ahmadi-Pour presenting at the University Booth on "MicroRV32: A #SpinalHDL based #RISC-V Implementation for #FPGAs" @agra_uni_bremen @DFKI #VerSys #scale4edge @BMBF_Bund @DateConference #DATEconference @risc_v #riscv

Rolf_Drechsler's tweet image. #DATE2021 - Sallar Ahmadi-Pour presenting at the University Booth on "MicroRV32: A #SpinalHDL based #RISC-V Implementation for #FPGAs" @agra_uni_bremen @DFKI #VerSys #scale4edge @BMBF_Bund @DateConference #DATEconference @risc_v #riscv
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leaflabs's profile picture. Research and engineering services firm focused on low level computing. We love hard problems and elegant solutions.
LeafLabs
 @leaflabs
Dec 9, 2022

Don't miss LeafLabs' Jeff Ciesielski presenting at the #SpinalHDL "Explore the SpinalHDL Landscape" webinar next Friday, December 16. He will be sharing how we're leveraging SpinalHDL to enable the rapid development of devices used for Neuroscience research!

leaflabs's tweet image. Don't miss LeafLabs' Jeff Ciesielski presenting at the #SpinalHDL "Explore the SpinalHDL Landscape" webinar next Friday, December 16. He will be sharing how we're leveraging SpinalHDL to enable the rapid development of devices used for Neuroscience research!
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Daniel_Grosse's profile picture. Professor for Complex Systems at @jkulinz. Interested in #EDA, #Verification, #FormalMethods, #RISCV, #VirtualPrototype, #SystemC.
Daniel Große
 @Daniel_Grosse
May 24, 2022

You are interested in #fuzzing your #SpinalHDL design? Than have a look at "SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs" presented by Katharina Ruep tomorrow at European Test Symposium 2022. 👉 ics.jku.at/files/2022ETS_…

Daniel_Grosse's tweet image. You are interested in #fuzzing your #SpinalHDL design? Than have a look at "SpinalFuzz: Coverage-guided fuzzing for SpinalHDL designs" presented by Katharina Ruep tomorrow at European Test Symposium 2022. 👉 ics.jku.at/files/2022ETS_…
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