#gpuprogramming hasil pencarian

Day 2 of #GPUProgramming: >read an article about shared memory >learnt about registers……..Global memory >almost blacked out from elaboration of L1 & L2 iykyk >”repetition”to digest what I just learnt for about 900k milliseconds

tatavishnurao's tweet image. Day 2 of #GPUProgramming:
>read an article about shared memory 
>learnt about registers……..Global memory
>almost blacked out from elaboration of L1 & L2 iykyk
>”repetition”to digest what I just learnt for about 900k milliseconds

"Need better CUDA textbooks. 'Programming Massively Parallel Processors' is a good intro. I've created C/CUDA C implementations for first 3 chapters. Check book & my GitHub repo for details. #CUDA #GPUprogramming"

taras_y_sereda's tweet image. "Need better CUDA textbooks. 'Programming Massively Parallel Processors' is a good intro. I've created C/CUDA C implementations for first 3 chapters. Check book & my GitHub repo for details. #CUDA #GPUprogramming"

"10 days into CUDA, and I’ve earned my first badge of honor! 🚀 From simple kernels to profiling, every day is a step closer to mastering GPU computing. Onward to 100! #CUDA #GPUProgramming #100DaysOfCUDA"

shlok_fx's tweet image. "10 days into CUDA, and I’ve earned my first badge of honor! 🚀 From simple kernels to profiling, every day is a step closer to mastering GPU computing. Onward to 100! #CUDA #GPUProgramming #100DaysOfCUDA"

Each common operation is implemented as its own .cu file—modular. intriguing. #CUDA #NVIDIA #GPUProgramming #libcudf

yasunrik's tweet image. Each common operation is implemented as its own .cu file—modular. intriguing.
#CUDA #NVIDIA #GPUProgramming #libcudf

Day 3 of GPU programming At this rate I'll be writing custom inference kernels for AI by next month. The gap between PyTorch abstractions and bare metal isn't as wide as it seemed. #CUDA #GPUProgramming #MachineLearning

LearnInShadows's tweet image. Day 3 of GPU programming

At this rate I'll be writing custom inference kernels for AI by next month. The gap between PyTorch abstractions and bare metal isn't as wide as it seemed. 
#CUDA #GPUProgramming #MachineLearning
LearnInShadows's tweet image. Day 3 of GPU programming

At this rate I'll be writing custom inference kernels for AI by next month. The gap between PyTorch abstractions and bare metal isn't as wide as it seemed. 
#CUDA #GPUProgramming #MachineLearning

Day 2 of GPU programming Never knew addition needs so much code 😂 Starting to get the hang of program_id. Used Gemini 3.0 to generate pseudocode since I'm new to GPU programming and didn't want full code. Lets hope this momentum continues

LearnInShadows's tweet image. Day 2 of GPU programming

Never knew addition needs so much code 😂

Starting to get the hang of program_id.  
Used Gemini 3.0 to generate pseudocode since I'm new to GPU programming and didn't want full code.
Lets hope this momentum continues
LearnInShadows's tweet image. Day 2 of GPU programming

Never knew addition needs so much code 😂

Starting to get the hang of program_id.  
Used Gemini 3.0 to generate pseudocode since I'm new to GPU programming and didn't want full code.
Lets hope this momentum continues


Day 3 of #GPUProgramming: >in-depth of what shared memory is capable of >read about techniques by which these concepts optimize their performance >synchronization of threads during matmul >realized it took ~1.5 hours to digest this stuff >tried to code matrix multiplication…

tatavishnurao's tweet image. Day 3 of #GPUProgramming:
>in-depth of what shared memory is capable of
>read about techniques by which these concepts optimize their performance
>synchronization of threads during matmul
>realized it took ~1.5 hours to digest this stuff
>tried to code matrix multiplication…

⚡ Built my own graphics engine: Asthrarisine Sounds fun? Reality = invisible meshes, memory bugs & shader headaches. But here’s what made it work: #OpenGL #GraphicsEngine #GPUProgramming #GLTF #GameDev #ShaderProgramming


#GPUProgramming - Day 07: 🔧 #CPU Hazards 101 🚧: Ever heard of #Register Renaming & Out-of-Order Execution? They tackle structural hazards, ensuring smooth sailing for instructions. Watch out for Data Hazards (#RAW, #WAR, #WAW) in #MIPS, but fear not! #COA #LearnInPublic

hridoy_bashir's tweet image. #GPUProgramming - Day 07:
🔧 #CPU Hazards 101 🚧: Ever heard of #Register Renaming & Out-of-Order Execution? They tackle structural hazards, ensuring smooth sailing for instructions. Watch out for Data Hazards (#RAW, #WAR, #WAW) in #MIPS, but fear not!
#COA #LearnInPublic
hridoy_bashir's tweet image. #GPUProgramming - Day 07:
🔧 #CPU Hazards 101 🚧: Ever heard of #Register Renaming & Out-of-Order Execution? They tackle structural hazards, ensuring smooth sailing for instructions. Watch out for Data Hazards (#RAW, #WAR, #WAW) in #MIPS, but fear not!
#COA #LearnInPublic
hridoy_bashir's tweet image. #GPUProgramming - Day 07:
🔧 #CPU Hazards 101 🚧: Ever heard of #Register Renaming & Out-of-Order Execution? They tackle structural hazards, ensuring smooth sailing for instructions. Watch out for Data Hazards (#RAW, #WAR, #WAW) in #MIPS, but fear not!
#COA #LearnInPublic

#GPUProgramming - Day 02: 🔄 Exploring CPU architectures! #RISC, like #ARM & #Power, opts for efficiency with many registers. #CISC, exemplified by #Intel 8086, prioritizes simplicity, offering diverse, complex instructions. RISC excels in energy efficiency. #COA #LearnInPublic

hridoy_bashir's tweet image. #GPUProgramming - Day 02:
🔄 Exploring CPU architectures! #RISC, like #ARM & #Power, opts for efficiency with many registers. #CISC, exemplified by #Intel 8086, prioritizes simplicity, offering diverse, complex instructions. RISC excels in energy efficiency.
#COA #LearnInPublic
hridoy_bashir's tweet image. #GPUProgramming - Day 02:
🔄 Exploring CPU architectures! #RISC, like #ARM & #Power, opts for efficiency with many registers. #CISC, exemplified by #Intel 8086, prioritizes simplicity, offering diverse, complex instructions. RISC excels in energy efficiency.
#COA #LearnInPublic

#GPUProgramming - Day 03: 🧠 CPUs: Processors adapt with DISA. #CPU's core duo - Control Unit & Datapath. Datapath: Registers, ALU, Buses, Multiplexers – a data symphony! 🔄 Follow the Instruction Execution Cycle: Fetch ➡️Decode➡️Execute➡️Store➡️ Update PC. 🕹️ #LearnInPublic

hridoy_bashir's tweet image. #GPUProgramming - Day 03:
🧠 CPUs: Processors adapt with DISA. 
#CPU's core duo - Control Unit & Datapath. 
Datapath: Registers, ALU, Buses, Multiplexers – a data symphony! 
🔄 Follow the Instruction Execution Cycle: 
Fetch ➡️Decode➡️Execute➡️Store➡️ Update PC. 🕹️ 
#LearnInPublic
hridoy_bashir's tweet image. #GPUProgramming - Day 03:
🧠 CPUs: Processors adapt with DISA. 
#CPU's core duo - Control Unit & Datapath. 
Datapath: Registers, ALU, Buses, Multiplexers – a data symphony! 
🔄 Follow the Instruction Execution Cycle: 
Fetch ➡️Decode➡️Execute➡️Store➡️ Update PC. 🕹️ 
#LearnInPublic

#GPUProgramming - Day 01: 🚀 Exploring RISC architecture: Simplified, optimized instructions in one clock cycle. 🔄 Bye, CISC complexity! 🏎️ Registers rule, boosting speed. 🤖💡 Compiler-friendly design, slick pipelining for simultaneous processing! 🕵️‍♂️ #COA #RISC #LearnInPublic

hridoy_bashir's tweet image. #GPUProgramming - Day 01:
🚀 Exploring RISC architecture: Simplified, optimized instructions in one clock cycle. 🔄 Bye, CISC complexity! 🏎️ Registers rule, boosting speed. 🤖💡 Compiler-friendly design, slick pipelining for simultaneous processing! 🕵️‍♂️
#COA #RISC #LearnInPublic

#GPUProgramming - Day 08: 🚀 Explored #computerarchitecture today! 🖥️ Control Hazards tackle branch prediction, #Pentium FDIV bug a classic example. 💡 Memory #Hierarchy is key—#RAM, #cache levels (L1, L2, L3), and storage devices play crucial roles. 🔄🌐 #Memory #LearnInPublic

hridoy_bashir's tweet image. #GPUProgramming - Day 08:
🚀 Explored #computerarchitecture today! 🖥️ Control Hazards tackle branch prediction, #Pentium FDIV bug a classic example. 💡 Memory #Hierarchy is key—#RAM, #cache levels (L1, L2, L3), and storage devices play crucial roles. 🔄🌐 #Memory #LearnInPublic
hridoy_bashir's tweet image. #GPUProgramming - Day 08:
🚀 Explored #computerarchitecture today! 🖥️ Control Hazards tackle branch prediction, #Pentium FDIV bug a classic example. 💡 Memory #Hierarchy is key—#RAM, #cache levels (L1, L2, L3), and storage devices play crucial roles. 🔄🌐 #Memory #LearnInPublic

Day 4 of #GPUProgramming: >revised about warp behaviour & reduction basics >tried to code warp synchronisation >couldn’t do much because of semester end exams prep >well it is better to do something than nothing so that’s a wrap for today

tatavishnurao's tweet image. Day 4 of #GPUProgramming:
>revised about warp behaviour & reduction basics
>tried to code warp synchronisation 
>couldn’t do much because of semester end exams prep
>well it is better to do something than nothing so that’s a wrap for today

Day 3 of #GPUProgramming: >in-depth of what shared memory is capable of >read about techniques by which these concepts optimize their performance >synchronization of threads during matmul >realized it took ~1.5 hours to digest this stuff >tried to code matrix multiplication…

tatavishnurao's tweet image. Day 3 of #GPUProgramming:
>in-depth of what shared memory is capable of
>read about techniques by which these concepts optimize their performance
>synchronization of threads during matmul
>realized it took ~1.5 hours to digest this stuff
>tried to code matrix multiplication…


#GPUProgramming - Day 06: 🔍 Diving into computer architecture! 🖥️ Structural hazards arise when hardware resources are in high demand, causing contention among instructions. Data hazards? RAW, WAR, WAW – the battle for data paths and registers! 💡 #COA #LearnInPublic

hridoy_bashir's tweet image. #GPUProgramming - Day 06:
🔍 Diving into computer architecture! 🖥️ Structural hazards arise when hardware resources are in high demand, causing contention among instructions. Data hazards? RAW, WAR, WAW – the battle for data paths and registers! 💡
#COA #LearnInPublic

#GPUProgramming - Day 04: 🕰️ Dive into processor architectures! 🧠 Single-cycle execution, one clock cycle per instruction, demands a versatile datapath. 🔄 Multi-cycle instructions break it down for a more intricate dance with time. ⏳ #ComputerArchitecture #LearnInPublic 🚀

hridoy_bashir's tweet image. #GPUProgramming - Day 04:
🕰️ Dive into processor architectures! 🧠 Single-cycle execution, one clock cycle per instruction, demands a versatile datapath. 🔄 Multi-cycle instructions break it down for a more intricate dance with time. ⏳ #ComputerArchitecture #LearnInPublic 🚀
hridoy_bashir's tweet image. #GPUProgramming - Day 04:
🕰️ Dive into processor architectures! 🧠 Single-cycle execution, one clock cycle per instruction, demands a versatile datapath. 🔄 Multi-cycle instructions break it down for a more intricate dance with time. ⏳ #ComputerArchitecture #LearnInPublic 🚀

#GPUProgramming - Day 05: 🚀 Pipelining in computer architecture boosts performance by dividing instruction execution into stages. Techniques like forwarding, branch prediction, and superscalar processors enhance parallelism.💻🌐 #ComputerArchitecture #Pipelining #LearnInPublic

hridoy_bashir's tweet image. #GPUProgramming - Day 05:
🚀 Pipelining in computer architecture boosts performance by dividing instruction execution into stages. Techniques like forwarding, branch prediction, and superscalar processors enhance parallelism.💻🌐
#ComputerArchitecture #Pipelining #LearnInPublic

was getting bored ... So I made custom CUDA kernels for vector addition with 6 levels of optimization from naive implementation to shared , tiling till vectorized ops here is the link github.com/AmanSwar/Kerne… #CUDA #GPUProgramming #AI

Compile_Conquer's tweet image. was getting bored ...
So I made custom CUDA kernels for vector addition with 6 levels of optimization
from naive implementation to shared , tiling till vectorized ops
here is the link
github.com/AmanSwar/Kerne…
#CUDA #GPUProgramming #AI

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Tidak ada hasil untuk "#gpuprogramming"
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