#pipelinec 검색 결과
So... I've made a little "LoRa" (CSSS) beacon demo with #ULX3S and #PipelineC ! Ramp Nco ("SF6") -> Sine / Cosine NCO's => 2nd Order Delta sigma DAC => digital iq mixer -> output #sdr #fpga #rf #csss #lora #dsp #dac #sigmadelta #alldigitaltx
#QAM16 Modulator made with #PipelineC simulation with #GHDL and cocotb! Raised Cosine filter with 0.35 rollof and 4 samples/symbol ! #fpga #qam #sdr #dsp
Blinking the #ULX3S led with #PipelineC ! @pipelinec_hdl is a Magic tool that turns C into HDL 🔥 #fpga #ledblink #lattice
Ethernet Loopback Works! Made with #PipelineC! Thanks for the help Julian Kemmerer @pipelinec_hdl ! #100baseT #ethernet on a #ulx3s #fpga using a #lan7820 board!
#PipelineC Raised Cosine FIR Filter simulation with GDHL + cocotb! QAM modulator comming next... #fpga #ghdl #vhdl #rf #dsp #sdr
Blinking leds on the #StratixV #FPGA using C code with #PipelineC ! #gsd5 #altera #quartus #intel #microsoft #catapult #sotoreypeak
Following the previous post about the #FPGA #16APSK Modulator made with #PipelineC ... Here are some real world tests using the ULX3S Board! #dsp #sdr #apsk #hdl #ulx3s #dac #deltasigma #rf
Nice... We did something similar for #PipelineC and ended up doing the FFT in hardware too! @pipelinec_hdl
Want a fast, simple, and small integer FFT implementation geared for 32-bit (ARM + RISC-V) processors? I have largely rewritten one of the more popular fix_fft implementations and got the OK by most recent maintainers to put it under the MIT license. github.com/cnlohr/fix32_f…
1/4 as many RV32I @risc_v cores for same or better performance. Threads share #PipelineC auto pipelined ~15 stage kernel() hardware function to offload shader compute. CPU is now bottleneck for moving data around from RAM to pipeline and back. #FPGA #HDL #RTL #graphics #riscv
Four RV32I @risc_v cores totaling ~333M IPS do work with a 480p frame buffer 🤓. 20 threads, ~software rendering, but focus isn't on CPU core, next up: experiments with custom accelerator pipelines to offload compute 😏 #PipelineC #FPGA #HDL #RTL #graphics #riscv
Use #PipelineC to listen to FM #radio with an #FPGA #SDR! Huge thanks to @DutraCGI and @Darkknight512 for making this first version a great learning process. And @deepwavedigital for the fantastic #hardware platform and workplace <3 fosstodon.org/@pipelinec/112… #hdl #hls #asic
So... I made a blog... The first official post is about the #PipelineC #NCO I was developing last week! @ico_TC paulo-d2000.github.io/en-us/2023/10/… #FPGA #SDR #DSP
#AD Taking Care of Your Pipelines: Why It's Important dynagard.info/taking-care-of… #pipelinec
Nice... We did something similar for #PipelineC and ended up doing the FFT in hardware too! @pipelinec_hdl
Want a fast, simple, and small integer FFT implementation geared for 32-bit (ARM + RISC-V) processors? I have largely rewritten one of the more popular fix_fft implementations and got the OK by most recent maintainers to put it under the MIT license. github.com/cnlohr/fix32_f…
Following the previous post about the #FPGA #16APSK Modulator made with #PipelineC ... Here are some real world tests using the ULX3S Board! #dsp #sdr #apsk #hdl #ulx3s #dac #deltasigma #rf
Ethernet Loopback Works! Made with #PipelineC! Thanks for the help Julian Kemmerer @pipelinec_hdl ! #100baseT #ethernet on a #ulx3s #fpga using a #lan7820 board!
So... I've made a little "LoRa" (CSSS) beacon demo with #ULX3S and #PipelineC ! Ramp Nco ("SF6") -> Sine / Cosine NCO's => 2nd Order Delta sigma DAC => digital iq mixer -> output #sdr #fpga #rf #csss #lora #dsp #dac #sigmadelta #alldigitaltx
1/4 as many RV32I @risc_v cores for same or better performance. Threads share #PipelineC auto pipelined ~15 stage kernel() hardware function to offload shader compute. CPU is now bottleneck for moving data around from RAM to pipeline and back. #FPGA #HDL #RTL #graphics #riscv
C code that each thread is running: github.com/JulianKemmerer… C code and #PipelineC play nicely together for when hardware and software need to share interfaces/types 🤓
github.com
PipelineC/examples/risc-v/gcc_test/frame_buffer_test.c at 5ec0258cae9bf18d2073be2fb59b4a29b3cd98e0...
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC
Code for the barrel #RISCV CPUs in #PipelineC github.com/JulianKemmerer…
github.com
PipelineC/examples/risc-v/barrel_risc-v.c at master · JulianKemmerer/PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC
Four RV32I @risc_v cores totaling ~333M IPS do work with a 480p frame buffer 🤓. 20 threads, ~software rendering, but focus isn't on CPU core, next up: experiments with custom accelerator pipelines to offload compute 😏 #PipelineC #FPGA #HDL #RTL #graphics #riscv
Blinking the #ULX3S led with #PipelineC ! @pipelinec_hdl is a Magic tool that turns C into HDL 🔥 #fpga #ledblink #lattice
Use #PipelineC to listen to FM #radio with an #FPGA #SDR! Huge thanks to @DutraCGI and @Darkknight512 for making this first version a great learning process. And @deepwavedigital for the fantastic #hardware platform and workplace <3 fosstodon.org/@pipelinec/112… #hdl #hls #asic
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